AD9804 データシートの表示（PDF） - Analog Devices

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AD9804

Complete 10-Bit 18 MSPS CCD Signal Processor

Analog Devices 

AD9804

PROGRAMMING THE SERIAL INTERFACE

Table I. VGA Gain Register Contents (Default Value x096)

MSB

D9

D8

D7

D6

D5

D4

D3

D2

D1

0

0

0

1

0

1

1

1

1

•

•

•

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

LSB

D0

Gain (dB)

1

6.0

•

•

•

0

39.965

1

40.0

SDATA

tDS

SCK

RNW ADDRESS BITS

0

1

0

0

tDH

DATA BITS

0

D0 D1

D2 D3 D4

D5 D6 D7

tLS

SL

NOTES:

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. RNW = READ, NOT WRITE. SET LOW FOR WRITE OPERATION.

3. INTERNAL VGA GAIN REGISTER UPDATE OCCURS AT SL RISING EDGE.

Figure 3. Serial Write Operation

D8 D9 D10

tLH

SDATA

tDS

SCK

RNW ADDRESS BITS

1

1

0

0

tDH

DATA BITS

0

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

tDV

tLS

tLH

SL

NOTES:

1. RNW = READ, NOT WRITE. SET HIGH FOR READ OPERATION.

2. THE RNW BIT AND THE FOUR ADDRESS BITS MUST BE WRITTEN TO THE AD9804. SDATA IS LATCHED ON SCK RISING EDGES.

3. SERIAL DATA FROM VGA GAIN REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES.

Figure 4. Serial Readback Operation

–6–

REV. 0

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