AD9858 データシートの表示（PDF） - Analog Devices
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AD9858 Datasheet PDF : 32 Pages
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AD9858
ELECTRICAL SPECIFICATIONS
Unless otherwise noted, VDD = 3.3 V ± 5%, CPVDD = 5 V ± 5%, RSET = 2 kΩ, CPISET = 2.4 kΩ, reference clock frequency = 1 GHz.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS1
Reference Clock Frequency Range (Divider Off )
Reference Clock Frequency Range (Divider On)
Duty Cycle at 1 GHz
Input Capacitance
Input Impedance
Input Sensitivity
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
26 MHz fOUT
65 MHz fOUT
126 MHz fOUT
375 MHz fOUT
180 MHz fOUT (700 MHz REFCLK)
Narrow-Band SFDR2
40 MHz fOUT (±15 MHz)
40 MHz fOUT (±1 MHz)
40 MHz fOUT (±50 kHz)
100 MHz fOUT (±15 MHz)
100 MHz fOUT (±1 MHz)
100 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz)
180 MHz fOUT (±1 MHz)
180 MHz fOUT (±50 kHz)
360 MHz fOUT (±15 MHz)
360 MHz fOUT (±1 MHz)
360 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz, 700 MHz REFCLK)
180 MHz fOUT (±1 MHz, 700 MHz REFCLK)
180 MHz fOUT (±50 kHz, (700 MHz REFCLK)
OUTPUT PHASE NOISE CHARACTERISTICS (AT 103 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
OUTPUT PHASE NOISE CHARACTERISTICS (AT 403 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
Temp Test Level Min
Typ Max
Unit
Full
VI
Full
VI
25°C V
25°C V
25°C IV
Full
VI
10
1000
MHz
20
2000
MHz
42
50 58
%
3
pF
1500
Ω
–20
+5
dBm
Full
Full
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
10
5
20
–10
0.5
1
100
AVDD – 1.5
40
+10
15
1
1.5
AVDD + 0.5
Bits
mA
% FS
μA
LSB
LSB
kΩ
V
Full
V
70
dBc
Full
V
66
dBc
Full
V
62
dBc
Full
V
58
dBc
Full
IV
52
dBc
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
82
dBc
87
dBc
88
dBc
81
dBc
82
dBc
86
dBc
74
dBc
84
dBc
85
dBc
75
dBc
85
dBc
86
dBc
65
dBc
80
dBc
84
dBc
Full
V
Full
V
Full
V
–147
–150
–152
dBc/Hz
dBc/Hz
dBc/Hz
Full
V
Full
V
Full
V
–133
–137
–140
dBc/Hz
dBc/Hz
dBc/Hz
Rev. C | Page 3 of 32
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