AD9858 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9858 Datasheet PDF : 32 Pages
| |||
AD9858
Parameter
OUTPUT PHASE NOISE CHARACTERISTICS
(AT 100 MHz IOUT With 700 MHz REFCLK)
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency
Phase Detector Frequency (Divide-by-4 Enabled)3
Charge Pump Sink and Source Current4
Fast Lock Current (Acquisition Only)
Open-Loop Current (Acquisition Only)
Sink and Source Current Absolute Accuracy5
Sink and Source Current Matching5
Input Sensitivity PDIN and DIVIN (50 Ω)6
Input Impedance PDIN and DIVIN (Single-Ended)
Phase Noise @ 100 MHz Input Frequency
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
Charge Pump Output Range7
MIXER
IFOUT 8
fRF
fLO
Conversion Gain
LO Level
RF Level
Input IP3
1 dB Input Compression Power9
Input Impedance (Single-Ended)
LO
RF
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic 1 Voltage
Logic 0 Voltage
POWER DISSIPATION
PDISS (Worst-Case Conditions—Everything on
PFD Input Frequency 150 MHz)
PDISS (DAC and DDS Core Only Worst-Case)
PDISS (Power-Down Mode)
PDISS Mixer Only
PDISS PFD and CP (at 100 MHz) Only
Temp Test Level Min
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
V
Full
V
Full
IV
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
V
Full
V
Full
VI
Full
VI
Full
VI
Full
VI
Full
V
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
–125
–140
–148
–150
–150
–150
–15
0.0
–10
–20
5
–3
2.0
2.8
Typ Max
150
400
4
7
30
2.5
1
0
1
110
140
148
CPVDD
400
2
2
3.5
+5
9
1
1
0.8
12
12
3
0.4
2
2.5
1.7 2
65 100
60 75
350 435
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
MHz
mA
mA
mA
%
%
dBm
kΩ
dBc/Hz
dBc/Hz
dBc/Hz
V
MHz
GHz
GHz
dB
dBm
dBm
dBm
dBm
kΩ
kΩ
V
V
μA
μA
pF
V
V
W
W
mW
mW
mW
Rev. C | Page 4 of 32
Share Link: 