AD9864 データシートの表示（PDF） - Analog Devices
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AD9864 Datasheet PDF : 44 Pages
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AD9864
DIGITAL SPECIFICATIONS
Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature Test Level Min
Typ
Max Unit
DECIMATOR
Decimation Factor1
Full
IV
48
960
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
Full
V
50%
fCLKOUT
Full
IV
1.2 dB
Full
IV
88
dBm
SPI-READ OPERATION (See Figure 30)
PC Clock Frequency
PC Clock Period (tCLK)
PC Clock High (tHI)
PC Clock Low (tLOW)
PC to PD Setup Time (tDS)
PC to PD Hold Time (tDH)
PE to PC Setup Time (tS)
PC to PE Hold Time (tH)
SPI-WRITE OPERATION2 (See Figure 29)
PC Clock Frequency
PC Clock Period (tCLK)
PC Clock High (tHI)
PC Clock Low (tLOW)
PC to PD Setup Time (tDS)
PC to PD Hold Time (tDH)
PC to PD (or DOUTB) Data Valid Time (tDV)
PE to PD Output Valid to Hi-Z (tEZ)
SSI2 (See Figure 32)
CLKOUT Frequency
CLKOUT Period (tCLK)
CLKOUT Duty Cycle (tHI, tLOW)
CLKOUT to FS Valid Time (tV)
CLKOUT to DOUT Data Valid Time (tDV)
CMOS LOGIC INPUTS3
Logic 1 Voltage (VIH)
Logic 0 Voltage (VIL)
Logic 1 Current (IIH)
Logic 0 Current (IIL)
Input Capacitance
CMOS LOGIC OUTPUTS2, 3, 4
Logic 1 Voltage (VOH)
Logic 0 Voltage (VOL)
Full
IV
Full
IV
100
Full
IV
45
Full
IV
45
Full
IV
2
Full
IV
2
Full
IV
5
Full
IV
5
10 MHz
ns
ns
ns
ns
ns
ns
ns
Full
IV
10 MHz
Full
IV
100
ns
Full
IV
45
ns
Full
IV
45
ns
Full
IV
2
ns
Full
IV
2
ns
Full
IV
3
ns
Full
IV
8
ns
Full
IV
0.867
26 MHz
Full
IV
38.4
1153 ns
Full
IV
33
50
67 ns
Full
IV
–1
+1 ns
Full
IV
–1
+1 ns
Full
IV
VDDH – 0.2
V
Full
IV
0.5 V
Full
IV
10
µA
Full
IV
10
µA
Full
IV
3
pF
Full
IV
Full
IV
VDDH – 0.2
V
0.2 V
1 Programmable in steps of 48 or 60.
2 CMOS output mode with CLOAD = 10 pF and Drive Strength = 7.
3 Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V.
4 IOL = 1 mA; specification is also dependent on drive strength setting.
Rev. 0 | Page 6 of 44
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