AD9865 データシートの表示（PDF） - Analog Devices

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AD9865

Broadband Modem Mixed-Signal Front End

Analog Devices 

AD9865

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter

Tx PATH INTERFACE (See Figure 53)

Input Nibble Rate (2× Interpolation)

Input Nibble Rate (4× Interpolation)

Tx Data Setup Time (tDS)

Tx Data Hold Time (tDH)

Rx PATH INTERFACE1 (See Figure 54)

Output Nibble Rate

Rx Data Valid Time (tDV)

Rx Data Hold Time (tDH)

Temp

Full

Full

Full

Full

Full

Full

Full

Test Level

II

II

II

II

II

II

II

Min

Typ

Max

Unit

20

160

MSPS

10

100

MSPS

2.5

ns

1.5

ns

10

160

MSPS

3

ns

0

ns

1 CLOAD =5 pF for digital data outputs.

EXPLANATION OF TEST LEVELS

I 100% production tested.

II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.

VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. A | Page 8 of 48

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