AD9913(Rev0) データシートの表示（PDF） - Analog Devices
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AD9913 Datasheet PDF : 32 Pages
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AD9913
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external
reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.
Table 1.
Parameter
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier
REF_CLK Input Divider Frequency
VCO Oscillation Frequency
PLL Lock Time
External Crystal Mode
CMOS Mode
Input Capacitance
Input Impedance (Differential)
Input Impedance (Single-Ended)
Duty Cycle
REF_CLK Input Level
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
AC Voltage Compliance Range
SPURIOUS-FREE DYNAMIC RANGE
SERIAL PORT TIMING CHARACTERISTICS
SCLK Frequency
SCLK Pulse Width
SCLK Rise/Fall Time
Data Setup Time to SCLK
Data Hold Time to SCLK
Data Valid Time in Read Mode
PARALLEL PORT TIMING CHARACTERISTICS
PCLK Frequency
PCLK Pulse Width
PCLK Rise/Fall Time
Address/Data Setup Time to PCLK
Address/Data Hold Time to PCLK
Data Valid Time in Read Mode
IO_UPDATE/PROFILE(2:0) TIMING
Setup Time to SYNC_CLK
Hold Time to SYNC_CLK
Conditions/Comments
Min Typ Max Unit
Disabled
Enabled
Full temperature range
VCO1
VCO2
25 MHz reference clock, 10× PLL
VIH
VIL
250 MHz
250 MHz
83 MHz
16
250 MHz
100
250 MHz
60
μs
25
MHz
0.9
V
0.65 V
3
pF
2.7
kΩ
1.35
kΩ
45
55 %
355
1000 mV p-p
Refer to Figure 6
4.6 mA
−14
−6 %FS
+0.1 μA
−0.4
+0.4 LSB
−0.5
+0.5 LSB
±400
mV
Low
High
32 MHz
17.5
ns
3.5
ns
2
ns
5.5
ns
0
ns
22 ns
Low
High
33 MHz
10
ns
20
ns
2
ns
3.0
ns
0.3
ns
8
ns
0.5
ns
1
SYNC_CLK cycles
Rev. 0 | Page 3 of 32
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