AD9920ABBCZ データシートの表示（PDF） - Analog Devices
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AD9920ABBCZ Datasheet PDF : 112 Pages
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AD9920A
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, fCLI = 40.5 MHz, unless otherwise noted.
Table 4.
Parameter
MASTER CLOCK
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal
Pixel Position 0
SLAVE MODE SPECIFICATIONS
VD Falling Edge to HD Falling Edge
HD Falling Edge to CLI Rising Edge
HD Falling Edge to CLO Rising Edge
CLI Rising Edge to SHPLOC
AFE
SHPLOC Sample Edge to SHDLOC
Sample Edge
SHDLOC Sample Edge to SHPLOC
Sample Edge
AFE Pipeline Delay
AFE CLPOB Pulse Width
DATA OUTPUTS
Output Delay from DCLK Rising Edge
Pipeline Delay from SHP/SHD
Sampling to Data Output
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
TIMING CORE SETTING RESTRICTIONS
Inhibited Region for SHP Edge
Location1
Inhibited Region for SHP or SHD with
Respect to H-Clocks2, 3, 4
RETIME = 0, MASK = 0
Test Conditions/
Comments
See Figure 18
See Figure 105
Only valid if OSC_RST = 0
Only valid if OSC_RST = 1
Internal sample edge
See Figure 23
See Figure 23
See Figure 26
See Figure 25
Must not exceed CLI
frequency
See Figure 23
See Figure 23 and
Figure 24
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
Inhibited Region for DOUTPHASE Edge See Figure 23
Location
Symbol Min
Typ Max
tCONV
tCLIDLY
24.7
0.8 × tCONV/2
tCONV/2
6
1.2 × tCONV/2
Unit
ns
ns
ns
tVDHD
tHDCLI
tHDCLO
tCLISHP
tS1
tS2
tOD
0
VD period − tCONV ns
3
tCONV − 2
ns
3
tCONV − 2
ns
3
tCONV − 2
ns
0.8 × tCONV/2 tCONV/2 tCONV − tS2
0.8 × tCONV/2 tCONV/2 tCONV − tS1
16
2
20
ns
ns
Cycles
Pixels
1
ns
16
Cycles
fSCLK
tLS
tLH
tDS
tDH
tSHPINH
40.5
10
10
10
10
50
MHz
ns
ns
ns
ns
62
Edge
location
tSHDINH
tSHDINH
tSHPINH
tSHPINH
tDOUTINH
HxNEGLOC − 14
HxPOSLOC − 14
HxNEGLOC − 14
HxPOSLOC − 14
SHDLOC + 1
HxNEGLOC − 2
HxPOSLOC − 2
HxNEGLOC − 2
HxPOSLOC − 2
SHDLOC + 12
Edge
location
Edge
location
Edge
location
Edge
location
Edge
location
1 Applies only to slave mode operation. The inhibited area for SHP is needed to meet the timing requirement for tCLISHP for proper H-counter reset operation.
2 When the HBLKRETIME bits (Address 0x35, Bits[3:0]) are enabled, the inhibit region for the SHD location changes to the inhibit region for the SHP location.
3 When the HBLK masking polarity registers (V-sequence Register 0x18[24:21]) are set to 0, the H-edge reference becomes HxNEGLOC.
4 The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1; Mode 2 = H1, H2; Mode 3 = H1, H3; and 3-Phase Mode = Phase 1,
Phase 2, and Phase 3.
Rev. B | Page 7 of 112
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