AD9925 データシートの表示（PDF） - Analog Devices
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AD9925 Datasheet PDF : 96 Pages
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AD9925
SPECIFICATIONS
Table 1.
Parameter
Min
Typ
TEMPERATURE RANGE
Operating
–25
Storage
–65
POWER SUPPLY VOLTAGES
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1 to H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
2.7
3.0
2.7
3.0
2.7
3.0
2.7
3.0
2.7
3.0
2.7
3.0
V-DRIVER SUPPLY VOLTAGES
VDVDD (V-Driver Input Logic Supply)
2.7
3.0
VH1, VH2 (V-Driver High Supply for 3-Level Outputs)
10.5
15.0
VM1, VM2 (V-Driver Mid Supply for 3-Level and 2-Level Outputs)
VL1, VL2 (V-Driver Low Supply for 3-Level and 2-Level Outputs)
–1.0
0.0
–10.0
–7.5
POWER DISSIPATION—AFETG Section Only (see Figure 9 for Power Curves)
36 MHz, 3.0 V Supply, 100 pF Load on Each H1 to H4 Output, 20 pF RG Load
370
Standby 1 Mode
10
Standby 2 Mode
10
Standby 3 Mode
1
Power from HVDD Only1
130
Power from RGVDD Only
10
Power from AVDD Only
105
Power from TCVDD Only
42
Power from DVDD Only
57
Power from DRVDD Only
26
POWER DISSIPATION—V-Driver Section Only (VDVDD, VH, VL)
Normal Operation (VH = 15.0 V, VL = −7.5 V)2
60
Standby 1 Mode2
70
Standby 2 Mode2
70
Standby 3 Mode2
110
MAXIMUM CLOCK RATE (CLI)
36
Max
Unit
+85
°C
+150
°C
3.6
V
3.6
V
3.6
V
3.6
V
3.6
V
3.6
V
3.6
V
16.0
V
+3.0
V
–6.0
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
MHz
1 The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD.
Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. CLOAD is the total capacitance seen by all H-outputs.
2 The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measure-
ment, in each mode of operation. Load conditions are described in the Vertical Driver Specifications section.
Rev. A | Page 3 of 96
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