AD9925BBCZ データシートの表示（PDF） - Analog Devices
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AD9925BBCZ Datasheet PDF : 96 Pages
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AD9925
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
AD9925
E
TOPVIEW
F
(Not to Scale)
G
H
J
K
L
Figure 3. 96-Lead CSPBGA Package Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
E1, F2, F3
HVSS
G2, G3
HVSS
F1
H1
G1
H2
H1, H2, H3
HVDD
J2, J3
HVDD
J1
H3
K1
H4
K2, L2
RGVSS
L3
RG
L4
RGVDD
K3, K4
TCVDD
J4
CLO
J5
SYNC
K5, L5
TCVSS
J6
CLI
K6, L7
AVSS
L6
CCDIN
K7
AVDD
L8
REFT
L9
REFB
J7
MSHUT
J8
SUBCK
K8
VL
K9
VH2
L10
RSTB
K11
SL
J11
SCK
J10
SDI
J9
V8
K10
V7
H9
STROBE
H11
VM2
H10
V6
G10
V4
G11
V2
G9
VD
Type1
P
P
DO
DO
P
P
DO
DO
P
DO
P
P
DO
DI
P
DI
P
AI
P
AO
AO
DO
DO
P
P
DI
DI
DI
DI
VO2
VO2
DO
P
VO2
VO2
VO2
DIO
Description2
H1 to H4, HL Driver Ground
H1 to H4, HL Driver Ground
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1 to H4, HL Driver Supply
H1 to H4, HL Driver Supply
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Reset Gate Clock
RG Driver Supply
Analog Supply for Timing Core
Clock Output for Crystal
External System Sync Input
Analog Ground for Timing Core
Reference Clock Input
Analog Ground for AFE
CCD Signal Input
Analog Supply for AFE
Voltage Reference Top Bypass
Voltage Reference Bottom Bypass
Mechanical Shutter Pulse
CCD Substrate Clock (E Shutter)
V-Driver Low Supply
V-Driver High Supply 2
Reset Bar, Active Low Pulse
3-Wire Serial Load Pulse
3-Wire Serial Clock
3-Wire Serial Data Input
CCD Vertical Transfer Clock
CCD Vertical Transfer Clock
Strobe Pulse
V-Driver Mid Supply 2
CCD Vertical Transfer Clock
CCD Vertical Transfer Clock
CCD Vertical Transfer Clock
Vertical Sync Pulse (Input in Slave Mode, Output in Master Mode)
Rev. A | Page 9 of 96
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