AD9927BBCZ データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9927BBCZ Datasheet PDF : 100 Pages
| |||
AD9927
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.
Table 4.
Parameter
Symbol Min
Typ
MASTER CLOCK (See Figure 16)
CLI Clock Period
tCONV
25
CLI High/Low Pulse Width
10
12.5
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
VD FALLING EDGE TO HD FALLING EDGE IN SLAVE MODE (See Figure 89) tVDHD
0
AFE CLPOB PULSE WIDTH (See Figure 23 and Figure 33)1, 2
2
20
AFE SAMPLE LOCATION (See Figure 17 and Figure 20)1
SHP Sample Edge to SHD Sample Edge
tS1
11
12.5
DATA OUTPUTS (See Figure 21 and Figure 22)
Output Delay from DCLK Rising Edge
tOD
1
Inhibited Area for DOUTPHASE Edge Location
tDOUTINH SHDLOC + 1
Max
15
VD period − 5 × tCONV
SHDLOC + 15
Pipeline Delay from SHP/SHD Sampling to DOUT
16
SERIAL INTERFACE (See Figure 97)
Maximum SCK Frequency (Must Not Exceed CLI Frequency)
fSCLK
40
SL to SCK Setup Time
tLS
10
SCK to SL Hold Time
tLH
10
SDATA Valid to SCK Rising Edge Setup
tDS
10
SCK Falling Edge to SDATA Valid Hold
tDH
10
Unit
ns
ns
ns
ns
Pixels
ns
ns
Edge
location
Cycles
MHz
ns
ns
ns
ns
1 Parameter is programmable.
2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Rev. 0 | Page 6 of 100
Share Link: 