AD9929 データシートの表示（PDF） - Analog Devices

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AD9929

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

AD9929

TABLE OF CONTENTS

Specifications..................................................................................... 3

Digital Specifications ................................................................... 4

Analog Specifications................................................................... 4

Timing Specifications .................................................................. 5

Vertical Driver Specifications ..................................................... 5

Terminology ...................................................................................... 7

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Functional Descriptions.......................... 9

Equivalent Input Circuits .............................................................. 10

System Overview ............................................................................ 18

Theory of Operation ...................................................................... 19

Modes of Operation ................................................................... 19

Horizontal and Vertical Counters ............................................ 19

CLI Input Clock Divider............................................................ 19

Gray Code Registers................................................................... 19

Serial Interface Timing .............................................................. 20

Analog Front End Description and Operation....................... 22

Precision Timing, High Speed Timing Generation ............... 23

H Driver and RG Outputs ......................................................... 23

Digital Data Outputs.................................................................. 26

External Synchronization (Master Mode)................................... 27

Horizontal and Vertical Synchronous Timing............................ 28

Special Note about the HDLEN Register ................................ 28

Horizontal Clamping and Blanking ............................................. 29

Controlling CLPOB Clamp Pulse Timing .............................. 29

Controlling CLPOB Clamp Pulse Outputs ............................. 30

REVISION HISTORY

Revision A

2/04—Data Sheet Changed from Rev. 0 to Rev. A

Replaced Figure....................................................................................21

1/04—Revision 0: Initial Version

H1 and H2 Blanking .................................................................. 31

VGATE Masking of XV1 to XV4 and CLPOB Outputs............ 33

Vertical Timing Generation .......................................................... 34

Creating Vertical Sequences...................................................... 34

Special Vertical Sweep Mode Operation ................................. 39

Special Vertical Timing (SPATS).............................................. 40

V1 to V4 and SUBCK Output Polarities ..................................... 43

Timing Control............................................................................... 46

Electronic Shutter Timing Control .......................................... 46

VSG Timing ................................................................................ 48

VSUB Timing.............................................................................. 49

MSHUT Timing ......................................................................... 50

Strobe Timing ............................................................................. 52

Digital I/O States for Different Operating Conditions.............. 53

Power Supply Sequencing ............................................................. 54

Recommended Power-Up Supply Sequencing....................... 54

Recommended Power-Down Supply Sequencing ................. 54

Initial Start-Up Sequence .......................................................... 55

Standby Mode Operation .......................................................... 56

Shut-Down Mode Operation.................................................... 57

Applications Where the CLI Clock Frequency Changes

During Operation....................................................................... 58

Circuit Layout Information........................................................... 60

Outline Dimensions ....................................................................... 62

Ordering Guide .......................................................................... 62

Rev. A | Page 2 of 64

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