AD9929 データシートの表示（PDF） - Analog Devices
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AD9929 Datasheet PDF : 64 Pages
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AD9929
TIMING SPECIFICATIONS
Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min Typ Max Unit
MASTER CLOCK, CLI
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulse Width
13.9
ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
ns
AFE CLAMP PULSES1
CLPOB Pulse Width
4
10
Pixels
AFE SAMPLE LOCATION1 (See Figure 17)
SHP Sample Edge to SHD Sample Edge
TS1
20
25
Pixels
DATA OUTPUTS
Output Delay from DCLK1 Rising Edge (See Figure 19)
tOD
9
ns
Pipeline Delay from SHP/SHD Sampling (See Figure 70)
9
Cycles
SERIAL INTERFACE (See Figure 10 and Figure 11)
tDV
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tOD
10
ns
1 Parameter is programmable.
VERTICAL DRIVER SPECIFICATIONS
Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = −7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND,
fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
VIH
0.8 (VDD)
VDD
V
Low Level Input Voltage
VIL
0
0.3 (VDD)
V
Propagation Delays, Rise/Fall Times and Output Currents
V1 and V3 Outputs (See Figure 43)
Delay Times
VL to VM1
tPLM1
100
ns
VM1 to VH1
tPMH
100
ns
VH1 to VM1
tPHM
50
ns
VM1 to VL
tPML1
50
ns
Rise Times
VL to VM1
tR1
500
ns
VM1 to VH1
tR2
500
ns
Fall Times
VH1 to VM1
tF1
500
ns
VM1 to VL
tF2
500
ns
Output Currents
V1 or V3 @ VL = −7.25 V
10.0
mA
V1 or V3 @ VM1 = −0.25 V
−5.0
mA
V1 or V3 @ VM1 = +0.25 V
5.0
mA
V1 or V3 @ VH1 = +14.75 V
−7.2
mA
Rev. A | Page 5 of 64
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