AD9937KCP データシートの表示（PDF） - Analog Devices

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AD9937KCP

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

AD9937

8-BIT REG

ADDRESS [7:0]

12-BIT START

ADDRESS [11:0]

12-BIT END

ADDRESS[11:0]

32-BIT DATA 0 [31:0]

32-BIT DATA N [31:0]

SDA

8 BIT

ADDRESS

START LOCATION

ADDRESS

END LOCATION

ADDRESS

DATA 0 [31:0]

DATA N [31:0]

SCK

SLD

1

1

1

2

1. ALL SLD PULSES ARE IGNORED UNTIL THE LAST BIT OF THE LAST DATA N WORD IS CLOCKED IN.

2. THE SLD PULSE MUST BE ASSERTED HIGH WHEN ALL SDA DATA TRANSMISSIONS HAVE BEEN COMPLETED.

Figure 6. System and Mode Register Writes

Internal Power-On Reset Circuitry

After power-on, the AD9937 automatically resets all internal

registers and performs internal calibration procedures. This

takes approximately 1 ms to complete. During this time, normal

clock signals and serial write operations may occur. However,

serial register writes are ignored until the internal reset opera-

tion is completed.

VD Synchronous and Asynchronous Register Operation

There are two types of control registers, VD synchronous and

VD asynchronous, as indicated in the Address column of Table I.

Register writes to synchronous and asynchronous type registers

operate differently as described in the following sections. All

writes to system, Mode_A, and Mode_B registers occur

asynchronously.

Asynchronous Register Operation

For asynchronous register writes, SDA data is stored directly

into the serial register at the rising edge of SLK. As a result,

register operation begins immediately after the register LSB has

been latched in on the rising edge of SCK.

VD Synchronous Register Operation

For VD synchronous type registers, SDA data is temporarily

stored in a buffer register upon completion of clocking in the

last register LSB. This data is held in the temporary buffer

register until the next rising edge of VD is applied. Once the

next rising edge of VD occurs, the buffered register data is

loaded into the serial register, and register operation begins.

See Figure 7.

Control registers at addresses 0x08, 0x09, 0x10, 0x11, and 0x12

are VD synchronous type registers.

OPERATION OF VD SYNCHRONOUS TYPE

REGISTER WRITES BEGIN AT THE NEXT VD

RISING EDGE.

VD

HD

VCKM

PROGRAMMING VD SYNCHRONOUS

TYPE REGISTERS MUST BE COMPLETED

AT LEAST FOUR VCKM CYCLES BEFORE

THE RISING EDGE OF VD.

Figure 7. VD Synchronous Type Register Writes

REV. 0

–19–

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