AD9937 データシートの表示（PDF） - Analog Devices
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AD9937 Datasheet PDF : 44 Pages
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AD9937
Addr
0
1
Bit
Bit
Breakdown Width
(23:0)
24
0
1
Default
0
0
(23:1)
2
(1:0)
23
2
0
2
(23:3)
1
0
21
3
(7:0)
8
8
1
9
1
10
1
11
1
12
1
13
1
14
1
(16:15)
2
17
1
18
1
(23:19)
5
0x80
1
0
0
0
0
0
0
0
0
1
4
0
1
2
3
1
0
1
0
1
0
1
0
4
1
0
5
(23:6)
1
0
18
5
(5:0)
6
(11:6)
6
(17:12)
6
(19:18)
2
0x00
0x24
0x00
0x00
20
1
21
1
22
1
23
1
6
(5:0)
6
(11:6)
6
(17:12)
6
(23:18)
6
7
(2:0)
3
0
1
0
–
0x00
0x20
0x00
0x10
4
(5:3)
(8:6)
(23:9)
(23:1)
3
4
3
4
15
23
Table I. Control Register Map
Register
Name
Function
SW_RESET
Software Reset = 000000 (Reset All Registers to Default).
OUTCONT_REG Internal OUTCONT Signal Control (0 = Digital Outputs held
at fixed dc level, 1 = Normal Operation).
Unused
AFE_STBY
DIG_STBY
Unused
AFE Standby (0 = Full Standby, 1 = Normal Operation,
2/3 = Reference Standby).
Digital Standby (0 = Full Standby, 1 = Normal Operation).
REFBLACK
Black Clamp Level.
BC_EN
1 = Black Clamp Enable.
TESTMODE
This register should always be set to 0.
TESTMODE
This register should always be set to 0.
PBLK_LEVEL
0 = Blank to 0, 1 = Blank to Clamp Level (REFBLACK).
TRISTATEOUT 0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated.
RETIMEOUT_BAR 0 = Retime Data Outputs, 1 = Do Not Retime Data Outputs.
GRAY_ENCODE 1 = Gray Encode ADC Outputs.
TESTMODE
This register should always be set to 0.
TESTMODE
This register should always be set to 0.
TESTMODE
This register should always be set to 1.
Unused
VCKM_DIVIDE
H1BLKRETIME
LM_INVERT
TGOFD_INVERT
VDHD_INVERT
MASTER
Unused
VCKM Input Clock Divider (0 = VCKM, 1 = VCKM/2).
Retimes the H1 HBLK to Internal Clock.
LM Inversion Control (1 = Invert Programmed LM).
TG and OFD Inversion Control (1 = Invert Programmed TG
and ODF).
VD and HD Inversion Control (1 = Invert Programmed VD
and HD; Note that Internal VD/HD Are HI Active).
Operating Mode (0 = Slave Mode, 1 = Master Mode).
SHDLOC
SHPLOC
DOUTPHASE
DOUT_DELAY
VCLKMASK
VCLK_INVERT
DTEST
Unused
SHD Sample Location.
SHP Sample Location.
Data Output [9:0] and VCLK Phase Adjustment.
Data Output Clock Selection (0 = No Delay, 1 = ~4 ns, 2 = ~8 ns,
3 = ~12 ns).
VCLK Masking Control (1 = Mask).
1 = Invert VCLK.
1 = Internal Digital Signal Test Mode.
H1POSLOC
H1NEGLOC
RSPOSLOC
RSNEGLOC
H1 Positive Edge Location.
H1 Negative Edge Location.
RS Positive Edge Location.
RS Negative Edge Location.
H1DRV
H2DRV
RSDRV
Unused
Unused
H1A/B/C/D Drive Strength (0 = OFF, 1 = 1.75 mA, 2 = 3.5 mA,
3 = 5.25 mA, 4 = 7 mA, 5 = 8.75 mA, 6 = 10.5 mA, 7 = 12.25 mA).
H2A/B Drive Strength (see H1DRV).
RS Drive Strength (see H1DRV).
REV. 0
–9–
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