AD9942 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9942 Datasheet PDF : 36 Pages
| |||
TIMING SPECIFICATIONS
CL = 20 pF, fCLI = 40 MHz, serial timing in Figure 14 and Figure 15, unless otherwise noted. X = A, B.
Table 5.
Parameter
MASTER CLOCK (CLI_X) (See Figure 16)
CLI_X Clock Period
CLI_X High/Low Pulse Width
Delay from CLI_X to Internal Pixel Period Position (See Figure 16)
CLPOB_X PULSE WIDTH (Programmable)1
SAMPLE CLOCKS (See Figure 17)
SHP_X Rising Edge to SHD_X Rising Edge
DATA OUTPUTS (See Figure 19 and Figure 20)
Output Delay from Programmed Edge
Pipeline Delay
SERIAL INTERFACE
Maximum SCK_X Frequency
SL_X to SCK_X Setup Time
SCK to SL_X Hold Time
SDATA_X Valid to SCK_X Rising Edge Setup
SCK_X Falling Edge to SDATA_X Valid Hold
SCK_X Falling Edge to SDATA_X Valid Read
Symbol
tADC
tCLIDLY
tCOB
tS1
tOD
fSCLK
tLS
tLH
tDS
tDH
tDV
Min
Typ
Max
25.0
10.0
12.5
15.0
6
2
20
11.2
12.5
6
11
10
10
10
10
10
10
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
AD9942
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
Rev. A | Page 7 of 36
Share Link: 