AD9945(RevC) データシートの表示（PDF） - Analog Devices

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AD9945
(Rev.:RevC)

Complete 12-Bit 40 MHz CCD Signal Processor

Analog Devices 

AD9945

INTERNAL REGISTER DESCRIPTION

Table I. Internal Register Map

Register

Name

Address Bits

A3 A2 A1 A0

Data Bits

Function

Operation 0 0 0 0

Control

00 01

D0

D2, D1

D3

D5, D4

D6

D8, D7

D11 to D9

D0

D1

D2

D3

D4

D5

D6

D11 to D7

Software Reset (0 = Normal Operation, 1 = Reset all registers to default)

Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown)

OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF)

Test Mode. Should always be set to 00.

PBLK Blanking Level (0 = Blank Output to Zero, 1 = Blank to OB Clamp Level)

Low Gain Mode. Normally set to 00. To enable low gain mode, set to 11. When low gain mode

is enabled, VGA Gain register must be set to all zeroes.

Test Mode. Should always be set to 000.

SHP/SHD Input Polarity (0 = Active Low, 1 = Active High)

DATACLK Input Polarity (0 = Active Low, 1 = Active High)

CLPOB Input Polarity (0 = Active Low, 1 = Active High)

PBLK Input Polarity (0 = Active Low, 1 = Active High)

Three-State Data Outputs (0 = Outputs Active, 1 = Outputs Three-Stated)

Data Output Latching (0 = Latched by DATACLK, 1 = Latch is Transparent)

Data Output Coding (0 = Binary Output, 1 = Gray Code Output)

Test Mode. Should always be set to 00000.

Clamp Level 0 0 1 0

D7 to D0

OB Clamp Level (0 = 0 LSB, 255 = 255 LSB)

VGA Gain 0 0 1 1

D9 to D0

VGA Gain (0 = 6 dB, 1023 = 40 dB)

Startup

1101

D11 to D0

Required start-up write must be set to 0x838.

NOTE: All register values default to 0x0000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).

–8–

REV. C

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