AD9945(RevC) データシートの表示（PDF） - Analog Devices

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AD9945
(Rev.:RevC)

Complete 12-Bit 40 MHz CCD Signal Processor

Analog Devices 

SERIAL INTERFACE

AD9945

SDATA

tDS

SCK

A0

A1

A2 A3

D0 D1 D2

D3 D4

D5 D6 D7

tDH

D8 D9 D10 D11

tLS

tLH

SL

NOTES

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

3. ALL 12 DATA BITS D0 TO D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE

USED FOR THE UNDEFINED BITS.

Figure 4. Serial Write Operation

SDATA

DATA FOR STARTING

REGISTER ADDRESS

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5

DATA FOR NEXT

REGISTER ADDRESS

... ... ... D10 D11 D0 D1

D10 D11 D0 D1 D2

SCK

...

1 2 3 4 5 6 7 8 9 10

... 15 16 17 18

... 27 28 29 30 31

SL

...

...

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 12-BIT DATA-WORD (ALL 12 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.

Figure 5. Continuous Serial Write Operation to All Registers

...

REV. C

–9–

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