AD9945KCPZRL7 データシートの表示（PDF） - Analog Devices

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AD9945KCPZRL7

Complete 12-Bit 40 MHz CCD Signal Processor

Analog Devices 

CCD MODE TIMING

AD9945

CCD

SIGNAL

tID

N

tID

SHP

tS1

SHD

N+1

tS2

N+2

tCP

N+9

N+10

DATACLK

tOD

OUTPUT

N–10

N– 9

DATA

N– 8

N– 1

N

NOTES

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 8. CCD Mode Timing

CCD

SIGNAL

EFFECTIVE PIXELS

CLPOB

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS

EFFECTIVE PIXELS

PBLK

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

DUMMY BLACK

NOTES

1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 9. Typical CCD Mode Line Clamp Timing

EFFECTIVE DATA

REV. A

–11–

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