AD9945KCPRL7 データシートの表示（PDF） - Analog Devices

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AD9945KCPRL7

Complete 12-Bit 40 MHz CCD Signal Processor

Analog Devices 

AD9945

DEFINITIONS OF SPECIFICATIONS

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus, every

code must have a finite width. No missing codes guaranteed to

12-bit resolution indicates that all 4096 codes must be present

over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the output of the AD9945 from a true straight

line. The point used as zero scale occurs 1/2 LSB before the first

code transition. Positive full scale is defined as a level 1 1/2 LSB

beyond the last code transition. The deviation is measured from

the middle of each particular output code to the true straight line.

The error is then expressed as a percentage of the 2 V ADC full-

scale signal. The input signal is always appropriately gained up to

fill the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated in

LSB and represents the rms noise level of the total signal chain

at the specified gain setting. The output noise can be converted

to an equivalent voltage, using the relationship

1 LSB = (ADC Full Scale/2N codes)

where N is the bit resolution of the ADC. For the AD9945,

1 LSB is 0.5 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. This represents a very high frequency disturbance on the

AD9945’s power supply. The PSR specification is calculated

from the change in the data outputs for a given step change in

the supply voltage.

Internal Delay for SHP/SHD

The internal delay (also called aperture delay) is the delay that

occurs from the time when a sampling edge is applied to the

AD9945 until the actual sample of the input signal is held. Both

SHP and SHD sample the input signal during the transition from

low to high, so the internal delay is measured from each clock’s

rising edge to the instant the actual internal sample is taken.

EQUIVALENT INPUT CIRCUITS

DVDD

330⍀

AVDD

60⍀

DVSS

Figure 1. Digital Inputs—SHP, SHD,

DATACLK, CLPOB, PBLK, SCK, SL, SDATA

DVDD

DRVDD

DATA

AVSS

AVSS

Figure 3. CCDIN (Pin 22)

THREE-

STATE

DOUT

DVSS

DRVSS

Figure 2. Data Outputs—D0 to D11

–6–

REV. A

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