AD9991KCPRL データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD9991KCPRL

10-Bit CCD Signal Processor with Precision Timing ™ Generator

Analog Devices 

AD9991

12 edge locations. Table II shows the correct register values for

the corresponding edge locations.

Figure 7 shows the default timing locations for all of the high

speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9991

features on-chip output drivers for the RG and H1–H4 outputs.

These drivers are powerful enough to directly drive the CCD

inputs. The H-driver and RG current can be adjusted for optimum

rise/fall time into a particular load by using the DRVCONTROL

register (Addr 0x35). The 3-bit drive setting for each output is

adjustable in 4.1 mA increments, with the minimum setting of 0

equal to OFF or three-state, and the maximum setting of 7 equal

to 30.1 mA.

As shown in Figures 5, 6, and 7, the H2 and H4 outputs are

inverses of H1 and H3, respectively. The H1/H2 crossover volt-

age is approximately 50% of the output swing. The crossover

voltage is not programmable.

Digital Data Outputs

The AD9991 data output and DCLK phases are programmable

using the DOUTPHASE register (Addr 0x37, Bits [5:0]). Any

edge from 0 to 47 may be programmed, as shown in Figure 8a.

Normally, the DOUT and DCLK signals will track in phase based

on the DOUTPHASE register contents. The DCLK output phase

can also be held fixed with respect to the data outputs by chang-

ing the DCLKMODE register HIGH (Addr 0x37, Bit 6). In this

mode, the DCLK output will remain at a fixed phase equal to

CLO (the inverse of CLI) while the data output phase is still

programmable.

There is a fixed output delay from the DCLK rising edge to the

DOUT transition, called tOD. This delay can be programmed to

four values between 0 ns and 12 ns, by using the DOUTDELAY

register (Addr 0x037, Bits [8:7]). The default value is 8 ns.

The pipeline delay through the AD9991 is shown in Figure 8b.

After the CCD input is sampled by SHD, there is an 11-cycle

delay until the data is available.

Parameter

Polarity

Positive Edge

Negative Edge

Sampling Location

Drive Strength

Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD

Length

Range

Description

1b

High/Low

Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)

6b

0–47 Edge Location Positive Edge Location for H1, H3, and RG

6b

0–47 Edge Location Negative Edge Location for H1, H3, and RG

6b

0-47 Edge Location Sampling Location for Internal SHP and SHD Signals

3b

0–47 Current Steps Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)

Quadrant

I

II

III

IV

CCD

SIGNAL

RG

H1/H3

H2/H4

USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 6. 2-Phase H-Clock Operation

Table II. Precision Timing Edge Locations

Edge Location (Dec)

Register Value (Dec)

0 to 11

12 to 23

24 to 35

36 to 47

0 to 11

16 to 27

32 to 43

48 to 59

Register Value (Bin)

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

REV. 0

–11–

Share Link: