AD9991KCPRL データシートの表示（PDF） - Analog Devices

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AD9991KCPRL

10-Bit CCD Signal Processor with Precision Timing ™ Generator

Analog Devices 

AD9991

ANALOG SPECIFICATIONS (AVDD = 3.0 V, fCLI = 27 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Notes

CDS*

Allowable CCD Reset Transient

500

Max Input Range before Saturation

1.0

Max CCD Black Pixel Amplitude

±50

mV

V p-p

mV

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution

Gain Monotonicity

Gain Range

Min Gain (VGA Code 0)

Max Gain (VGA Code 1023)

1024

Guaranteed

6

42

Steps

dB

dB

BLACK LEVEL CLAMP

Clamp Level Resolution

Clamp Level

Min Clamp Level (Code 0)

Max Clamp Level (Code 255)

256

0

63.75

Steps

LSB

LSB

Measured at ADC output.

A/D CONVERTER

Resolution

Differential Nonlinearity (DNL)

No Missing Codes

Full-Scale Input Voltage

10

Bits

–1.0

±0.5

+1.0

LSB

Guaranteed

2.0

V

VOLTAGE REFERENCE

Reference Top Voltage (REFT)

Reference Bottom Voltage (REFB)

2.0

V

1.0

V

SYSTEM PERFORMANCE

Gain Accuracy

Low Gain (VGA Code 0)

5.0

5.5

Max Gain (VGA Code 1023)

40.5

41.5

Peak Nonlinearity, 500 mV Input Signal

0.2

Total Output Noise

0.25

Power Supply Rejection (PSR)

50

*Input signal characteristics defined as follows:

Includes entire signal chain.

6.0

dB

Gain = (0.0351 ϫ Code) + 6 dB

42.5

dB

%

12 dB gain applied.

LSB rms AC grounded input, 6 dB gain applied.

dB

Measured with step change on supply.

500mV TYP

RESET TRANSIENT

50mV MAX

OPTICAL BLACK PIXEL

1V MAX

INPUT SIGNAL RANGE

Specifications subject to change without notice.

–4–

REV. 0

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