AD9991KCP データシートの表示（PDF） - Analog Devices
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AD9991KCP Datasheet PDF : 60 Pages
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AD9991
PIN CONFIGURATION
D3 1
D4 2
D5 3
D6 4
D7 5
D8 6
D9 7
DRVDD 8
DRVSS 9
VSUB 10
SUBCK 11
V1 12
V2 13
V3 14
PIN 1
IDENTIFIER
AD9991
TOP VIEW
42 SDI
41 SL
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
34 CLO
33 TCVDD
32 TCVSS
31 RGVDD
30 RG
29 RGVSS
PIN FUNCTION DESCRIPTIONS1
Pin Mnemonic Type2 Description
Pin Mnemonic Type2 Description
1 D3
2 D4
3 D5
4 D6
5 D7
6 D8
7 D9
8 DRVDD
9 DRVSS
10 VSUB
11 SUBCK
12 V1
13 V2
14 V3
15 V4
16 V5
17 V6
18 VSG1
19 VSG2
20 VSG3
21 VSG4
22 VSG5
23 H1
24 H2
25 HVSS
26 HVDD
27 H3
28 H4
29 RGVSS
30 RG
31 RGVDD
32 TCVSS
33 TCVDD
34 CLO
35 CLI
DO Data Output
36 AVDD
P
Analog Supply for AFE
DO Data Output
37 CCDIN
AI CCD Signal Input
DO Data Output
38 AVSS
P
Analog Ground for AFE
DO Data Output
39 REFT
AO Voltage Reference Top Bypass
DO Data Output
40 REFB
AO Voltage Reference Bottom Bypass
DO Data Output
41 SL
DI 3-Wire Serial Load Pulse
DO Data Output (MSB)
42 SDI
DI 3-Wire Serial Data Input
P
Data Output Driver Supply
43 SCK
DI 3-Wire Serial Clock
P
Data Output Driver Ground
44 MSHUT DO Mechanical Shutter Pulse
DO CCD Substrate Bias
45 STROBE DO Strobe Pulse
DO CCD Substrate Clock (E-Shutter) 46 SYNC
DI External System Sync Input
DO CCD Vertical Transfer Clock 1
47 VD
DIO Vertical Sync Pulse
DO CCD Vertical Transfer Clock 2
(Input for Slave Mode,
DO CCD Vertical Transfer Clock 3
Output for Master Mode)
DO CCD Vertical Transfer Clock 4
48 DVSS
P
Digital Ground
DO CCD Vertical Transfer Clock 5
49 DVDD
P
Power Supply for VSG, V1–V6,
DO CCD Vertical Transfer Clock 6
HD/VD, MSHUT, STROBE,
DO CCD Sensor Gate Pulse 1
SYNC, and Serial Interface
DO CCD Sensor Gate Pulse 2
50 HD
DIO Horizontal Sync Pulse
DO CCD Sensor Gate Pulse 3
(Input for Slave Mode, Output for
DO CCD Sensor Gate Pulse 4
Master Mode)
DO CCD Sensor Gate Pulse 5
51 DCLK
DO Data Clock Output
DO CCD Horizontal Clock 1
52 NC
Not Internally Connected
DO CCD Horizontal Clock 2
53 NC
Not Internally Connected
P
H1–H4 Driver Ground
54 D0
DO Data Output (LSB)
P
H1–H4 Driver Supply
55 D1
DO Data Output
DO CCD Horizontal Clock 3
56 D2
DO Data Output
DO CCD Horizontal Clock 4
P
RG Driver Ground
NOTES
1See Figure 38 for circuit configuration.
DO CCD Reset Gate Clock
P
RG Driver Supply
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
P
Analog Ground for Timing Core
P
Analog Supply for Timing Core
DO Clock Output for Crystal
DI Reference Clock Input
–6–
REV. 0
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