AD9992 データシートの表示（PDF） - Analog Devices

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AD9992

12-Bit CCD Signal Processor with Precision Timing Generator

Analog Devices 

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Therefore,

every code must have a finite width. No missing codes

guaranteed to 12-bit resolution indicates that all 4096 codes

must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the output of the AD9992 from a true straight

line. The point used as zero scale occurs 0.5 LSB before the first

code transition. Positive full scale is defined as a level 1 LSB and

0.5 LSB beyond the last code transition. The deviation is measured

from the middle of each particular output code to the true straight

line. The error is then expressed as a percentage of the 2 V ADC

full-scale signal. The input signal is always appropriately amplified

to fill the full-scale range of the ADC.

AD9992

Total Output Noise

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB and represents the rms noise level of the total signal

chain at the specified gain setting. The output noise can be con-

verted to an equivalent voltage using the relationship

1 LSB = (ADC Full Scale/2n Codes)

where n is the bit resolution of the ADC. For the AD9992, 1 LSB

is 0.488 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. The PSR specification is calculated from the change in

data outputs for a given step change in the supply voltage.

Rev. C | Page 13 of 92

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