AD9992 データシートの表示（PDF） - Analog Devices
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AD9992 Datasheet PDF : 92 Pages
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AD9992
SPECIFICATIONS
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE INPUTS
AVDD (AFE Analog Supply)
TCVDD (Timing Core Supply)
CLIVDD (CLI Input Supply)
RGVDD (RG, HL Driver)
HVDD1/HVDD2 (H1 to H8 Drivers)1
DVDD (Digital Logic)
DRVDD (Parallel Data Output Drivers)
IOVDD (Digital I/O)
XVVDD (Vertical Output Drivers)
CP1P8 (CP Supply Input)
LDOIN (LDO Supply Input)
POWER SUPPLY CURRENTS—40 MHz OPERATION
AVDD (1.8 V)
TCVDD (1.8 V)
CLIVDD (3 V)
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
HVDD1/HVDD2 (3.3 V, 480 pF Total Load on H1 to H8)1
DVDD (1.8 V)
DRVDD (3 V, 10 pF Load on Each DOUT Pin)
IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)
XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Standby1 Mode
Standby2 Mode
Standby3 Mode
MAXIMUM CLOCK RATE (CLI)
Min Typ Max
Unit
−25
+85
°C
−65
+150 °C
1.6
1.8
2.0
V
1.6
1.8
2.0
V
1.6
3.0
3.6
V
2.7
3.0
3.6
V
2.7
3.0
3.6
V
1.6
1.8
2.0
V
1.6
3.0
3.6
V
1.6
3.0
3.6
V
1.6
3.0
3.6
V
1.6
1.8
2.0
V
2.25 3.0
3.6
V
27
mA
5
mA
1.5
mA
10
mA
59
mA
9.5
mA
6
mA
2
mA
2
mA
12
mA
5
mA
1.5
mA
40
MHz
1 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs.
Rev. C | Page 3 of 92
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