AD9992 データシートの表示（PDF） - Analog Devices
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AD9992 Datasheet PDF : 92 Pages
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AD9992
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.
Table 4.
Parameter
Symbol Min
Typ
MASTER CLOCK (See Figure 15)
CLI Clock Period
tCONV
25
CLI High/Low Pulse Width
10
12.5
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6
SLAVE MODE SPECIFICATIONS (See Figure 76)
VD Falling Edge to HD Falling Edge in Slave Mode
tVDHD
0
HD Edge to CLI Rising Edge (Only Valid if OSC_RSTB = LO)
HD Edge to CLO Rising Edge (Only Valid if OSC_RSTB = HI)
Inhibit Region for SHP Edge Location
AFE CLPOB PULSE WIDTH (See Figure 22 and Figure 32)1, 2
AFE SAMPLE LOCATION (See Figure 16 and Figure 19)1
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (See Figure 20 and Figure 21)
Output Delay from DCLK Rising Edge
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to DOUT
SERIAL INTERFACE (See Figure 83)
Maximum SCK Frequency (Must Not Exceed CLI Frequency)
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
INHIBIT REGION FOR SHP AND SHD WITH RESPECT TO H-CLOCK
EDGE PLACEMENT (see Figure 19) for H*POL = 1
RETIME = 0, MASK = 0
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
tHDCLI
tHDCLO
tSHPINH
tS1
tOD
tDOUTINH
fSCLK
tLS
tLH
tDS
tDH
tSHDINH
tSHDINH
tSHPINH
tSHPINH
3
3
48
2
20
11
12.5
1
SHDLOC + 1
16
40
10
10
10
10
H*NEGLOC – 15
H*POSLOC – 15
H*NEGLOC – 15
H*POSLOC – 15
Max
15
VD period − 5 ×
tCONV
tCONV − 2
tCONV − 2
63
SHDLOC + 15
H*NEGLOC – 0
H*POSLOC – 0
H*NEGLOC – 0
H*POSLOC – 0
1 Parameter is programmable.
2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Unit
ns
ns
ns
ns
ns
ns
Edge location
Pixels
ns
ns
Edge location
Cycles
MHz
ns
ns
ns
ns
Edge location
Edge location
Edge location
Edge location
Rev. C | Page 6 of 92
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