AD9995KCPRL データシートの表示（PDF） - Analog Devices

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AD9995KCPRL

12-Bit CCD Signal Processor with Precision Timing ™ Generator

Analog Devices 

AD9995

ANALOG SPECIFICATIONS (AVDD = 3.0 V, fCLI = 36 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Notes

CDS*

Allowable CCD Reset Transient

500

Max Input Range before Saturation

1.0

Max CCD Black Pixel Amplitude

±50

mV

V p-p

mV

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution

1024

Steps

Gain Monotonicity

Guaranteed

Gain Range

Min Gain (VGA Code 0)

6

dB

Max Gain (VGA Code 1023)

BLACK LEVEL CLAMP

Clamp Level Resolution

Clamp Level

Min Clamp Level (Code 0)

E Max Clamp Level (Code 255)

A/D CONVERTER

Resolution

Differential Nonlinearity (DNL)

T No Missing Codes

Full-Scale Input Voltage

VOLTAGE REFERENCE

E Reference Top Voltage (REFT)

Reference Bottom Voltage (REFB)

SYSTEM PERFORMANCE

L Gain Accuracy

Low Gain (VGA Code 0)

Max Gain (VGA Code 1023)

Peak Nonlinearity, 500 mV Input Signal

Total Output Noise

O Power Supply Rejection (PSR)

*Input signal characteristics defined as follows:

12

–1.0

5.0

40.5

S 500mV TYP

RESET TRANSIENT

50mV MAX

OPTICAL BLACK PIXEL

1V MAX

INPUT SIGNAL RANGE

OB Specifications subject to change without notice.

42

256

0

255

±0.5

+1.0

Guaranteed

2.0

2.0

1.0

5.5

6.0

41.5

42.5

0.2

0.8

50

dB

Steps

LSB

LSB

Measured at ADC output.

Bits

LSB

V

V

V

Includes entire signal chain.

dB

dB

%

LSB rms

dB

Gain = (0.0351  Code) + 6 dB

12 dB gain applied.

AC grounded input, 6 dB gain applied.

Measured with step change on supply.

–4–

REV. 0

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