ADA4841 データシートの表示（PDF） - Analog Devices

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ADA4841

Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier

Analog Devices 

ADA4841-1/ADA4841-2

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

Supply Voltage

Power Dissipation

Common-Mode Input Voltage

Differential Input Voltage

Storage Temperature Range

Operating Temperature Range

Lead Temperature

Junction Temperature

Rating

12.6 V

See Figure 5

−VS − 0.5 V to +VS + 0.5 V

±1.8 V

−65°C to +125°C

−40°C to +85°C

JEDEC J-STD-20

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is

specified for device soldered in circuit board for surface-mount

packages.

Table 5. Thermal Resistance

Package Type

θJA

8-lead SOIC_N

125

8-lead MSOP

130

6-Lead SOT-23

170

Unit

°C/W

°C/W

°C/W

Maximum Power Dissipation

The maximum safe power dissipation for the ADA4841-1/

ADA4841-2 is limited by the associated rise in junction

temperature (TJ) on the die. At approximately 150°C, which is

the glass transition temperature, the plastic changes its

properties. Even temporarily exceeding this temperature limit

may change the stresses that the package exerts on the die,

permanently shifting the parametric performance of the

amplifiers. Exceeding a junction temperature of 150°C for an

extended period can result in changes in silicon devices,

potentially causing degradation or loss of functionality.

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the die

due to the amplifier’s drive at the output. The quiescent power is

the voltage between the supply pins (VS) times the quiescent

current (IS).

PD = Quiescent Power + (Total Drive Power − Load Power)

( ) PD =

VS × IS

+

⎜⎜⎝⎛

VS

2

× VOUT

RL

⎟⎟⎠⎞ −

VOUT 2

RL

RMS output voltages should be considered. If RL is referenced

to −VS, as in single-supply operation, the total drive power is

VS × IOUT. If the rms signal levels are indeterminate, consider the

worst case, when VOUT = VS/4 for RL to midsupply.

PD

=

(VS

× IS

)+

(VS/4)2

RL

In single-supply operation with RL referenced to −VS, worst case

is VOUT = VS/2.

Airflow increases heat dissipation, effectively reducing θJA.

In addition, more metal directly in contact with the package

leads and through holes under the device reduces θJA.

Figure 5 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 8-lead MSOP

(145°C/W), 8-lead SOIC_N (125°C/W) and the 6-lead SOT-23

(170°C/W) on a JEDEC standard 4-layer board. θJA values are

approximations.

2.0

1.5

SOIC

MSOP

1.0

SOT-23

0.5

0

–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125

AMBIENT TEMPERATURE (°C)

Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 6 of 20

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