ADC1003S030 データシートの表示（PDF） - Integrated Device Technology

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ADC1003S030

(ADC1003S030 - ADC1003S050) Single 10 bits ADC

Integrated Device Technology 

Integrated Design Technology

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage

regulator

[7] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental

period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to

signal-to-noise ratio: SINAD = ENOB  6.02 + 1.76 dB.

[8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have

the same amplitude and the total amplitude of both signals provides full-scale to the converter.

[9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog

converter.

[10] Output data acquisition: the output data is available after the maximum delay time of td(o). For the 50 MHz version it is recommended to

have the lowest possible output load.

RT

ROT

code 1023

RL

RL

RM

IL

RL

Rlad

RL

code 0

ROB

RB

014aaa325

Fig 3. Explanation of Table 6 Table note 3

11. Additional information relating to Table 6

Table 7. Output coding and input voltage (typical values; referenced to AGND)

Code

Vi(a)(p-p) IR

(V)

Binary outputs D9 to D0

Two’s complement

outputs D9 to D0

Underflow < 1.455 0

00 0000 0000

10 0000 0000

0

1.455

1

00 0000 0000

10 0000 0000

1

-

1

00 0000 0001

10 0000 0001



-







511

2.43



01 1111 1111

11 1111 1111



-







1022

-

11

11 1111 1110

01 1111 1110

1023

3.405

1

11 1111 1111

01 1111 1111

Overflow

> 3.405 0

11 1111 1111

01 1111 1111

ADC1003S030_040_050_3

Product data sheet

Rev. 03 — 2 July 2012

© IDT 2012. All rights reserved.

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