ADG2128YCPZ-REEL7(RevA) データシートの表示（PDF） - Analog Devices
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ADG2128YCPZ-REEL7
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADG2128YCPZ-REEL7 Datasheet PDF : 28 Pages
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ADG2128
ADG2108 Limit at TMIN, TMAX
Parameter1 Conditions
Min
Max
Unit
t11
Standard mode
1000
ns
Fast mode
20 + 0.1 CBB
300
ns
High speed mode2
CB = 100 pF maximum 10
40
ns
CB = 400 pF maximum 20
80
ns
t11A
Standard mode
1000
ns
Fast mode
20 + 0.1 CBB
300
ns
High speed mode2
CB = 100 pF maximum 10
80
ns
CB = 400 pF maximum 20
160
ns
t12
Standard mode
300
ns
Fast mode
20 + 0.1 CBB
300
ns
High speed mode2
CB = 100 pF maximum 10
40
ns
CB = 400 pF maximum 20
80
ns
tSP
Fast mode
0
High speed mode2
0
50
ns
10
ns
Description
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
tFCL, fall time of SCL signal
Pulse width of suppressed spike
1 Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line; tR and tF are measured between
0.3 VDD and 0.7 VDD.
2 High speed I2C is available only in -HS models.
3 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
SCL
t6
t11
t2
t4
SDA
t7
P
S
S = START CONDITION
P = STOP CONDITION
t12
t3
t1
t6
t5
t10
S
Figure 2. Timing Diagram for 2-Wire Serial Interface
t8
t9
P
Rev. A | Page 8 of 28
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