ADIS16251 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

ADIS16251

Programmable Low Power Gyroscope

Analog Devices 

ADIS16251

TIMING SPECIFICATIONS

Table 2.

Parameter

fSCLK

tDATARATE

tDATASTALL

tCSHIGH

tCS

tDAV

tDSU

tDHD

tDF

tDR

tSFS

Description

Fast mode (SMPL_PRD ≥ 0x07; fS ≥ 64 Hz)

Normal mode (SMPL_PRD < 0x07; fS ≤ 56.9 Hz)

Data rate period, fast mode (SMPL_PRD ≥ 0x07; fS ≥ 64 Hz)

Data rate period, normal mode (SMPL_PRD < 0x07; fS ≤ 56.9 Hz)

Data stall time, fast mode (SMPL_PRD ≥ 0x07; fS ≥ 64 Hz)

Data stall time, normal mode (SMPL_PRD < 0x07; fS ≤ 56.9 Hz)

Chip select high

Chip select to clock edge

Data output valid after SCLK edge2

Data input setup time before SCLK rising edge

Data input hold time after SCLK rising edge

Data output fall time

Data output rise time

CS high after SCLK edge3

Flash update time (power supply must be within range)

Min1

0.01

0.01

32

42

9

12

1/fSCLK

48.8

24.4

48.8

5

50

Typ

Max1

Unit

2.5

MHz

1.0

MHz

μs

μs

μs

μs

ns

100

ns

ns

ns

5

12.5

ns min

5

12.5

ns min

ns

ms

1 Guaranteed by design; typical specifications are not tested or guaranteed.

2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked out after the falling edge of SCLK

and are governed by this specification.

3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.

tDATARATE

CS

SCLK

tDATASTALL

Figure 2. SPI Chip Select Timing

CS

SCLK

DOUT

DIN

tCS

1

*

MSB

W/R

2

3

4

5

6

tDAV

DB14

tDSU

DB13

DB12

tDHD

DB11

DB10

A5

A4

A3

A2

15

16

tSFS

DB2

DB1

LSB

D2

D1

LSB

*NOT DEFINED

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

Rev. A | Page 5 of 5

Share Link: