ADM1060ARU(RevPrJ) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
ADM1060ARU Datasheet PDF : 45 Pages
| |||
PRELIMINARY TECHNICAL DATA
ADM1060–SPECIFICATIONS1
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V2, TA = -40oC to 85oC, unless otherwise noted.)
Parameter
Min Typ Max
PROGRAMMABLE DRIVER
OUTPUTS
High Voltage (Charge Pump) Mode
(PDO’s 1 to 4)
Output Impedance, ROUT
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO’s 1 to 9)
VOH
440
10.5 12.5 14
10
12
20
2.4
VOL
ISINK
RPULLUP-
ISOURCE (VPn)
Weak Pull-up
4.5
VPU-0.3
0.4
1.2
2.0
20
20
2
Tristate Output Leakage Current
DIGITAL INPUTS
(GPI 1-4,WDI,A0,A1)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Input High Current, IIH
-1
Input Low Current, IIL
Input Capacitance
Programmable Pulldown Current, IPULLDOWN
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Output Low Voltage, VOL
PROGRAMMABLE DELAY BLOCK
Timeout
0
10
0.8
1
TBD
10
0.8
0.4
500
Units
k⍀
V
V
A
V
V
V
V
V
V
mA
k⍀
mA
A
V
V
A
A
pF
A
V
V
V
ms
Test Conditions/Comments
IOH=0
IOH=1A
2V<VOH<7V
VPU(Pullup to VDDCAP or
VPn)=2.7V, IOH=1mA
VPU to VPn=6.0V, IOH=0mA
VPU<=2.7V, IOH=1mA
IOL=2mA
IOL=10mA
IOL=15mA
Total Sink Current
Internal pullup
Current Load on any VPn pull-ups
(ie) total source current available
through any number of PDO pull-up
switches configured on to any one
VPDO=14.4V
Max. VIN=5.5V
Max. VIN=5.5V
VIN = 5.5V
VIN = 0
If known logic state required
IOUT = -3.0mA
16 programmable options on both
rising and falling edge
WATCHDOG TIMER INPUT
Timeout
0
12.8 s
8 programmable timeout options
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
400 KHz See Figure 8c
50
ns
See Figure 8c
4.7
µs
See Figure 8c
4.7
µs
See Figure 8c
4
µs
See Figure 8c
4.7
µs
See Figure 8c
4
µs
See Figure 8c
1000 ns
See Figure 8c
300 µs
See Figure 8c
250
ns
See Figure 8c
300
ns
See Figure 8c
NOTES
1 These are target specifications and subject to change.
2 At least one supply connected to VH or VPn must be >=3.0V
3 Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4 Timing specifications are tested at logic levels of VIL = 0.8V for a falling edge and VIH = 2.2V for a rising edge.
REV.PrJ 11/02
–5–
Share Link: 