ADM706T(RevA) データシートの表示（PDF） - Analog Devices

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ADM706T
(Rev.:RevA)

+3 V, Voltage Monitoring μP Supervisory Circuits

Analog Devices 

1.3V

PFI

+3V

VCC = +5V

TA = +25؇C

+1.2V

PFO

0V

500ns/DIV

Figure 10. PFI Assertion Response Time

VCC = +5V

TA = +25؇C

1.2V

PFO

+1.3V

PFI

+3V

0V

500ns/DIV

Figure 11. PFI Deassertion Response Time

VCC = VRT

TA = +25؇C

+3V

RESET

+3V

RESET

0V

0V

100ns/DIV

Figure 12. RESET, RESET Assertion

ADM706P/R/S/T, ADM708R/S/T

+3V

RESET

VCC = VRT

TA = +25؇C

+3V

RESET

0V

0V

100ns/DIV

Figure 13. RESET, RESET Deassertion

TA = +25؇C

+3V

VCC

+2V

+3V

RESET

0V

2␮s/DIV

Figure 14. ADM706/ADM708 RESET Response Time

APPLICATIONS

A typical operating Circuit is shown in Figure 15. The unregu-

lated dc input supply is monitored using the PFI input via the

resistive divider network. Resistors R1 and R2 should be selected

such that when the supply voltage drops below the desired level

(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold

thereby generating an interrupt to the µP. Monitoring the

preregulator input gives additional time to execute an orderly

shutdown procedure before power is lost.

UNREGULATED

DC

ADM666A

IN

OUT

GND

+3.3V

MANUAL

RESET

VCC

RESET

WDI

ADM706

PFI

WDO

MR

PFO

GND

VCC

RESET

I/O LINE

␮P

NMI

INTERRUPT

GND

Figure 15. Typical Application Circuit

REV. A

–7–

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