ADM8832(RevB) データシートの表示（PDF） - Analog Devices

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ADM8832
(Rev.:RevB)

Charge Pump Regulator for Color TFT Panel

Analog Devices 

ADM8832

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

VCC 1

VOUT 2

LDO_IN 3

+5VOUT 4

+5VIN 5

ADM8832

TOP VIEW

(Not to Scale)

15 C4–

14 C2+

13 C2–

12 C3+

11 C3–

E Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

T 1

VCC

Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor.

2

VOUT

Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to ground is required on

this pin.

E 3

LDO_IN

Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin.

4

+5VOUT

+5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 µF capacitor to ground is

required on this pin to stabilize the regulator.

5

+5VIN

+5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits.

L 6

LDO_ON/OFF Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage

doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the

use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into

the voltage tripler and doubler/inverter circuits of the ADM8832.

O 7

SHDN

Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and

enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V.

8

SCAN/BLANK Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge

pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the

S charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832.

9

CLKIN

External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump

circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current

consumption, thus saving power.

B 10

+15VOUT

+15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor is required on

this pin.

11, 12 C3−, C3+

External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended.

13, 14 C2−, C2+

External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended.

O 15, 16 C4−, C4+

External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended.

17

−10VOUT

−10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 µF capacitor is

required on this pin.

18

GND

Device Ground Pin.

19, 20 C1−, C1+

External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended.

Rev. B | Page 6 of 12

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