ADMC330 データシートの表示（PDF） - Analog Devices

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ADMC330

Single Chip DSP Motor Controller

Analog Devices 

ADMC330

Similar modifications can be made to Phases B and C using Bits

7 and 6, respectively, of the PWMSEG register. Six bits of the

PWMSEG register (Bits 0 . . . 5) are used to independently

enable/disable any individual PWM output pins. For example,

setting Bits 0 and 1 high disables PWM outputs CH and CL,

which keeps these outputs off over the full PWM period regard-

less of the value in the PWMCHC register. This feature is not

only useful for ECM control, but is also required in some space

vector modulation schemes. Modifications to the PWMSEG

register only become effective at the start of each PWM cycle. In

the transparent (default) mode, all bits in PWMSEG are set low.

Consider the situation shown in Figure 3 for operation of an

ECM with the AH and BL power devices active. The PWM

duty cycle registers, PWMCHA and PWMCHB, are programmed

with the appropriate on-time value. Since all three PWM regis-

ters must be written to trigger an update of the PWM, it is neces-

sary to write also to PWMCHC. For this example, the particular

value written to this register is unimportant. Subsequently,

crossover bit of the PWMSEG register for Phase B (Bit 7) is set

to enable crossover of the Phase B signals. The PWM outputs

for Phase C high and low, Phase B high and Phase A low are

disabled by setting Bits 0, 1, 2 and 5 of the PWMSEG register.

In this example, the appropriate value for the PWMSEG register

is 0x00A7. In addition, high side chopping of the signal AH is

enabled by setting Bit 8 of the PWMGATE register.

CENTER-

BASED

OUTPUTS

START

MIDPOINT

PWMCHA

PWMCHB

PWMDT

PWMDT

END

AH

AL

BH

BL

CH

CL

Figure 3. PWM Output Waveforms for an ECM with

Inverter Devices AH and BL Active

Known limitation of the ECM block. Modifying the PWMSEG

register while the PWM duty cycle transitions from a full-ON

state to any other state will cause both the high side and low

side devices to switch on for 50 ns. This potentially volatile

condition can be avoided by:

• Disabling the PWM channel outputs during the transition

from full-ON to any other state.

• Preventing the full-ON condition namely limiting PWMCHx to:

PWMCHx ≤ PWMTM –2 × (PWMDT + 1), with PWMPD = 0.

• Preventing a PWMSEG update operation during the transi-

tion from full-ON to any other state.

Gate Drive Unit

The Gate Drive Unit adds features that simplify the interface to

a variety of gate drive circuits for PWM inverters. If a trans-

former coupled power device gate drive amplifier is used, the

active PWM signal must be chopped at a high frequency of up

to 5 MHz. The chopped active PWM signals may be required

for the high side drivers only or for both high side and low side.

The gate drive chopping feature is enabled by Bits 8 and 9 of the

PWMGATE register. Setting Bit 8 enables a chopped PWM

signal on all high side output pins AH, BH and CH, setting

Bit 9 enables a chopped PWM signal on all low side output pins

AL, BL and CL. The gate chopping frequency is programmed

using Bits 0–5 of the PWMGATE register. The gate drive chop-

ping frequency is given by the following equation:

f chop

=

2

×

f HCLK

(GATETM

+1)

where GATETM is the 6-bit value in Bits 0 . . . 5 of the

PWMGATE register.

Depending on the type of power device gate drive circuit used,

either active high or active low, PWM signals will be required,

so an external PWM polarity pin is provided. The polarity of the

PWMPOL pin determines the active polarity of the PWM out-

put signals (i.e., a low PWMPOL pin means active low PWM).

This must be set by hardware because even though the ADMC330

will power up with all PWM outputs off, the correct polarity of

an off PWM signal is a function of the gate drive circuit only.

The level on the PWMPOL pin is available in Bit 2 of the

SYSSTAT register.

External PWM Trip

In fault conditions the power devices must be switched off as soon

as possible after the fault has been detected, hence an external

hardware PWM trip input is provided. A low going PWMTRIP

pulse will reset the PWM block which will disable all PWM

outputs. This will also generate a PWMTRIP interrupt signal

and cause a DSP interrupt. The PWMTRIP pin is accessible

through Bit 0 of SYSSTAT so that the DSP can determine

when the external fault has been cleared. At this point, a full

initialization of the PWM controller will be required to restart

the PWM.

ADC OVERVIEW

The analog input block is a 12-bit resolution analog data acqui-

sition system. A single slope type ADC is implemented by timing

the crossover between the analog input and a sawtooth refer-

ence ramp. A simple voltage comparator is used to latch the output

of a reference counter timer circuit when the crossover is detected.

There are seven input channels to the ADC of which three (V1,

V2 and V3) have dedicated comparators. The remaining four

inputs (VAUX0, VAUX1, VAUX2 and VAUX3) are multi-

plexed into the fourth comparator channel. This allows four

conversions per PWM period to be performed by the ADC. The

particular input signal that is fed to the fourth comparator input

is selected using the ADCMUX0 and ADCMUX1 bits of the

peripheral control register, MODECTRL. The settings of these

two control bits in order to select the appropriate auxiliary ana-

log input is shown in Table I.

–8–

REV. 0

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