ADMC401 データシートの表示（PDF） - Analog Devices
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ADMC401 Datasheet PDF : 60 Pages
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ADMC401–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (VDD = AVDD = 5 V ؎ 5%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C,
CLKIN = 13 MHz, unless otherwise noted)
Parameter
VDD
AVDD
TAMB
Digital Supply Voltage
Analog Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
4.75
5.25
4.75
5.25
–40
+85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Max
Unit
VIH
HI-Level Input Voltage1, 2, 3
@ VDD = max
2.0
V
VIL
LO-Level Input Voltage1, 2, 3
VOH
HI-Level Output Voltage1, 3, 4, 5, 6
@ VDD = min
@ VDD = min, IOH = –1.0 mA
0.8
V
2.4
V
VOL
LO-Level Output Voltage1, 3, 4, 5, 6
VOH
HI-Level Output Voltage5
@ VDD = min, IOH = –0.1 mA
VDD – 0.3
V
@ VDD = min, IOL = 2.0 mA
0.4
V
@ VDD = min, IOH = –10.0 mA
2.4
V
VOL
LO-Level Output Voltage5
IIH
HI-Level Input Current7
IIH
HI-Level Input Current8
@ VDD = min, IOL = 10.0 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = VDD max
1.2
V
10
µA
100
µA
IIH
HI-Level Input Current9
IIL
LO-Level Input Current7
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
10
µA
10
µA
IIL
LO-Level Input Current8
@ VDD = max, VIN = 0 V
10
µA
IIL
LO-Level Input Current9
IOZH
HI-Level Three-State Leakage Current10
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
100
µA
10
µA
IOZL
LO-Level Three-State Leakage Current10
@ VDD = max, VIN = 0 V
IDD
Digital Supply Current (Idle)11
@ VDD = max
IDD
Digital Supply Current (Dynamic)12
@ VDD = max
10
µA
40
mA
110
mA
IDD
Analog Supply Current
CI
Input Pin Capacitance13
@ AVDD = max
VIN = 2.5 V, fIN = 1 MHz,
60
mA
8
pF
CO
Output Pin Capacitance13, 14
TAMB = +25°C
VIN = 2.5 V, fIN = 1 MHz,
8
pF
TAMB = +25°C
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0–PIO11.
2Input only pins: PWMTRIP, PWMPOL, PWMSR, RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR
and PWD.
3Programmable I/O Pins (PIO0–PIO11).
4Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1, BG, BGH, PMS, DMS, BMS, RD, WR, PWDACK and A0–A13.
5Output pins: AH, AL, BH, BL, CH and CL.
6Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to V DD–0.3 V and GND+0.3 V assuming no dc loads.
7Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD.
8Input pins with internal pull-down PIO0–PIO11 and PWMTRIP.
9Input pins with internal pull-up, PWMPOL and PWMSR.
10Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
11Idle refers execution of the IDLE instruction. Deasserted pins are driven to V DD or GND. Current reflects device operation with CLKOUT disabled.
12Current reflects device operating with no output loads.
13Guaranteed but not tested.
14Output Pin Capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
–2–
REV. B
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