ADMC401 データシートの表示（PDF） - Analog Devices

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ADMC401

Single-Chip, DSP-Based High Performance Motor Controller

Analog Devices 

ADMC401

Parameter

Min

Max

Unit

Clock Signals

tCK is defined as 0.5tCKI. The ADMC401 uses an input clock

with a frequency equal to half the instruction rate; a 13 MHz

clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor

cycle (equivalent to 26 MHz). tCK values within the range of

0.5tCKI period should be substituted for all relevant timing

parameters to obtain specification value.

Example: tCKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.

Timing Requirements:

tCKI

tCKIL

tCKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

Switching Characteristics:

76.9

150

ns

20

ns

20

ns

tCKL

tCKH

tCKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

Control Signals

0.5tCK – 10

ns

0.5tCK – 10

ns

0

20

ns

Timing Requirement:

tRSP

RESET Width Low

5tCK1

ns

PWM Shutdown Signals

Timing Requirements:

tPWMTPW

PWMTRIP Width Low

tCK

ns

tPIOPWM

PIO Width Low

2tCK

ns

ADC Signals

Timing Requirements:

tCSI

Internal Convert Start Width High

2tCK

ns

tCSE

External Convert Start Width High

2tCK

ns

NOTE

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

CLKIN

CLKOUT

t CKI

t CKIH

t CKIL

t CKOH

t CKH

t CKL

Figure 1. Clock Signals

REV. B

–5–

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