ADMC401 データシートの表示（PDF） - Analog Devices

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ADMC401

Single-Chip, DSP-Based High Performance Motor Controller

Analog Devices 

ADMC401

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

tIFS

IRQx or FI Setup before CLKOUT Low1, 2, 3

tIFH

IRQx or FI Hold after CLKOUT High1, 2, 3

Switching Characteristics:

tFOH

Flag Output Hold after CLKOUT Low4

tFOD

Flag Output Delay from CLKOUT Low4

0.25tCK + 15

0.25tCK

0.5tCK – 7

ns

ns

ns

0.5tCK + 5

ns

NOTES

1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further

information on interrupt servicing.)

2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3IRQx = IRQ0 and IRQ1.

4Flag Output = FL1 and FO.

CLKOUT

FLAG

OUTPUTS

IRQx

FI

t FOD

t FOH

t IFH

t IFS

Figure 2. Interrupts and Flags

–6–

REV. B

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