Parameter
Memory Write
Switching Characteristics:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Data Setup before WR High
Data Hold after WR High
WR Pulsewidth
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
WR High to RD or WR Low
w = wait states × tCK.
Min
0.5tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 6
0.25tCK – 6
0.25tCK – 5
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
ADMC401
Max
Unit
ns
ns
ns
ns
ns
ns
0.25tCK + 7
ns
ns
ns
ns
CLKOUT
A0–A13
DMS, PMS
WR
D
RD
t WRA
t ASW
t CWR
t WP
t AW
t WDE
t DW
t WWR
t DH
t DDR
Figure 5. Memory Write
REV. B
–9–