ADM823MYRJZ-R7(RevC) データシートの表示（PDF） - Analog Devices

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ADM823MYRJZ-R7
(Rev.:RevC)

Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23

Analog Devices 

CIRCUIT DESCRIPTION

The ADM823/ADM824/ADM825 provide microprocessor

supply voltage supervision by controlling the reset input of the

microprocessor. Code execution errors are avoided during

power-up, power-down, and brownout conditions by asserting a

reset signal when the supply voltage is below a preset threshold.

Errors are also avoided by allowing supply voltage stabilization

with a fixed timeout reset pulse after the supply voltage rises

above the threshold. In addition, problems with microprocessor

code execution can be monitored and corrected with a watchdog

timer (ADM823/ADM824). By including watchdog strobe

instructions in microprocessor code, a watchdog timer can

detect whether the microprocessor code breaks down or becomes

stuck in an infinite loop. If this happens, the watchdog timer

asserts a reset pulse that restarts the microprocessor in a known

state. If the user detects a problem with the system’s operation, a

manual reset input is available (ADM823/ADM825) to reset the

microprocessor with an external push-button, for example.

RESET OUTPUT

The ADM823 features an active low, push-pull reset output, and

the ADM824/ADM825 feature dual active low and active high

push-pull reset outputs. For active low and active high outputs,

the reset signal is guaranteed to be logic low and logic high,

respectively, for VCC ≥ 1 V.

The reset output is asserted when VCC is below the reset

threshold (VTH), when MR is driven low, or when WDI is not

serviced within the watchdog timeout period (tWD). Reset

remains asserted for the duration of the reset active timeout

period (tRP) after VCC rises above the reset threshold, after MR

transitions from low to high, or after the watchdog timer times

out. Figure 15 illustrates the behavior of the reset outputs.

VCC

VCC

VTH

VTH

1V

0V

VCC

RESET

tRP

tRD

0V

VCC

RESET

1V

tRP

0V

tRD

Figure 15. Reset Timing Diagram

ADM823/ADM824/ADM825

MANUAL RESET INPUT

The ADM823/ADM825 feature a manual reset input (MR)

which, when driven low, asserts the reset output. When MR

transitions from low to high, reset remains asserted for the

duration of the reset active timeout period before deasserting.

The MR input has a 52 kΩ internal pull-up so that the input is

always high when unconnected. An external push-button

switch can be connected between MR and ground so that the

user can generate a reset. Debounce circuitry for this purpose is

integrated on chip. Noise immunity is provided on the MR

input and fast, negative-going transients of up to 100 ns (typical)

are ignored. A 0.1 μF capacitor between MR and ground

provides additional noise immunity.

WATCHDOG INPUT

The ADM823/ADM824 feature a watchdog timer that monitors

microprocessor activity. A timer circuit is cleared with every

low-to-high or high-to-low logic transition on the watchdog

input pin (WDI), which detects pulses as short as 50 ns. If the

timer counts through the preset watchdog timeout period (tWD),

reset is asserted. The microprocessor is required to toggle the

WDI pin to avoid being reset. Failure of the microprocessor to

toggle WDI within the timeout period, therefore, indicates a

code execution error, and the reset pulse generated restarts the

microprocessor in a known state.

In addition to logic transitions on WDI, the watchdog timer is

also cleared by a reset assertion due to an undervoltage condi-

tion on VCC or by MR being pulled low. When reset is asserted,

the watchdog timer is cleared and does not begin counting again

until reset is deasserted. The watchdog timer can be disabled by

leaving WDI floating or by three-stating the WDI driver.

VCC VCC

1V

0V

VCC

RESET

0V

VCC

WDI

0V

VTH

tRP

tWD

tRD

Figure 16. Watchdog Timing Diagram

Rev. C | Page 9 of 12

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