ADN2805 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
ADN2805 Datasheet PDF : 16 Pages
| |||
Data Sheet
ADN2805
Table 7. Internal Register Map1, 2
Reg. Name R/W Address D7
D6
D5
D4 D3
D2
FREQ0
R 0x0
MSB
FREQ1
R 0x1
MSB
FREQ2
R 0x2
0
MSB
RATE
R 0x3
COARSE_RD[8] MSB
Coarse Data Rate Readback
MISC
R 0x4
X
X
X
Static LOL
Data Rate
LOL Status Measure
Complete
CTRLA
W 0x8
fREF Range
Data Rate/DIV_fREF Ratio
CTRLB
W 0x9
Config Reset System 0
LOL MISC[4] Reset
Reset 0
MISC[2]
CTRLC
W 0x11
0
0
0
0
0
0
D1
D0
LSB
LSB
LSB
COARSE_RD[1]
X
COARSE_RD[0]
(LSB)
Measure Data Rate Lock to Reference
0
0
Squelch Mode
Output Boost
1 All writeable registers default to 0x00.
2 X = don’t care.
Table 8. Miscellaneous Register, MISC1
Static LOL
D7 D6 D5 D4
X X X 0 = waiting for next LOL
1 = static LOL until reset
1 X = don’t care.
LOL Status
D3
0 = locked
1 = acquiring
Data Rate Measurement Complete
D2
0 = measuring data rate
1 = measurement complete
Coarse Rate Readback LSB
D1 D0
X COARSE_RD[0]
Table 9. Control Register, CTRLA1
fREF Range
Data Rate/DIV_fREF Ratio
D7 D6
D5 D4 D3 D2
0 0 10 MHz to 20 MHz
00001
0 1 20 MHz to 40 MHz
00012
1 0 40 MHz to 80 MHz
00104
1 1 80 MHz to 160 MHz
n
2n
1 0 0 0 256
Measure Data Rate
D1
Set to 1 to measure data rate
Lock to Reference
D0
0 = lock to input data
1 = lock to reference clock
1 Where DIV_fREF is the divided down reference referred to the 10 MHz to 20 MHz band.
Table 10. Control Register, CTRLB
Configure LOL
Reset MISC[4]
D7
D6
0 = LOL pin normal operation Write a 1 followed by
1 = LOL pin is static LOL
0 to reset MISC[4]
System Reset
D5
Write a 1 followed by
0 to reset ADN2805
D4
Set to 0
Reset MISC[2]
D3
Write a 1 followed by
0 to reset MISC[2]
D2
Set to 0
D1
Set to 0
D0
Set to 0
Table 11. Control Register, CTRLC
D7
D6
D5
D4
Set to 0 Set to 0 Set to 0 Set to 0
D3
Set to 0
D2
Set to 0
Squelch Mode
D1
0 = SQUELCH DATAOUT and CLKOUT
1 = SQUELCH DATAOUT or CLKOUT
Output Boost
D0
0 = default output swing
1 = boost output swing
Rev. B | Page 9 of 16
Share Link: 