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ADN2807ACPZ-RL データシートの表示(PDF) - Analog Devices

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ADN2807ACPZ-RL Datasheet PDF : 21 Pages
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ADN2807
Data Sheet
Parameter
Test Conditions/Comments
Min
PHASE-LOCKED LOOP CHARACTERISTICS
PIN – NIN = 10 mV p-p
Jitter Transfer BW
OC-12
OC-3
Jitter Peaking
OC-12
OC-3
Jitter Generation
OC-12, 12 kHz to 5 MHz
OC-3, 12 kHz to 1.3 MHz
Jitter Tolerance
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Setup Time
Hold Time
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
TEST DATA DC INPUT CHARACTERISTICS4
(TDINP/N)
Peak-to-Peak Differential Input Voltage
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Input Current (SEL0 and SEL1 Only)5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
OC-12
30 Hz3
300 Hz
25 kHz
250 kHz3
OC-3
30 Hz3
300 Hz3
6500 Hz
65 kHz3
VSE (See Figure 7)
VDIFF (See Figure 7)
VOH
VOL, referred to VCC
20% to 80%
80% to 20%
TS (See Figure 3)
OC-12
OC-3
TH (See Figure 3)
OC-12
OC-3
At REFCLKP or REFCLKN
DC-coupled, single-ended
CML inputs
VIH
VIL
VIN = 0.4 V or VIN = 2.4 V
VIN = 0.4 V or VIN = 2.4 V
VOH, IOH = –2.0 mA
VOL, IOL = +2.0 mA
100
44
5.8
1.0
50
23.5
6.0
1.0
400
850
–0.60
750
3145
750
3150
0
100
2.0
–5
–5
2.4
1PIN and NIN should be driven differentially, ac-coupled for optimum sensitivity.
2PWD measurement made on quantizer outputs in BYPASS mode.
3Jitter tolerance measurements are equipment limited.
4TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.
Typ
140
48
0.004
0.002
0.02
0.02
488
975
VCC
VCC/2
0.8
Max
200
85
0.003
0.04
0.002
0.04
540
1100
–0.30
150
150
VCC
0.8
+5
+50
0.4
Unit
kHz
kHz
dB
dB
UI rms
UI p-p
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
mV
mV
V
V
ps
ps
ps
ps
ps
ps
V
mV
V
V
V
V
µA
µA
V
V
Rev. B | Page 4 of 21

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