ADN2811(RevA) データシートの表示（PDF） - Analog Devices

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ADN2811
(Rev.:RevA)

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2811

Parameter

Conditions

Min

Typ

CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing

Differential Output Swing

Output High Voltage

Output Low Voltage

Rise Time

VSE (See Figure 3)

VDIFF (See Figure 3)

VOH

VOL

20%–80%

Fall time

80%–20%

Setup Time

TS (See Figure 1)

OC-48

Hold Time

TH (See Figure 1)

OC-48

300

600

VCC – 0.6

140

150

455

910

VCC

84

84

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range

@ REFCLKP or REFCLKN

0

Peak-to-Peak Differential Input

100

Common-Mode Level

DC-Coupled, Single-Ended

VCC/2

TEST DATA DC INPUT

CHARACTERISTICS4 (TDINP/N)

CML Inputs

Peak-to-Peak Differential Input Voltage

0.8

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

Input Current

VIN = 0.4 V or VIN = 2.4 V

–5

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage

VOH, IOH = –2.0 mA

2.4

Output Low Voltage

VOL, IOL = +2.0 mA

NOTES

1PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2PWD measurement made on quantizer outputs in BYPASS mode.

3Measurement is equipment limited.

4TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

Specifications subject to change without notice.

Max

600

1200

VCC – 0.3

150

150

VCC

0.8

+5

0.4

Unit

mV

mV

V

V

ps

ps

ps

ps

V

mV

V

V

V

V

V

V

REV. A

–3–

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