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ADN2811

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

OC-48/OC-48 FEC Clock and Data Recovery

IC with Integrated Limiting Amp

ADN2811

FEATURES

PRODUCT DESCRIPTION

Meets SONET requirements for jitter transfer/generation/

tolerance

Quantizer sensitivity: 4 mV typical

Adjustable slice level: ±100 mV

1.9 GHz minimum bandwidth

Patented clock recovery architecture

Loss of signal detect range: 3 mV to 15 mV

The ADN2811 provides the receiver functions of quantization,

signal level detect, and clock and data recovery at OC-48 and

OC-48 FEC rates. All SONET jitter requirements are met,

including jitter transfer, jitter generation, and jitter tolerance. All

specifications are quoted for −40°C to +85°C ambient

temperature, unless otherwise noted.

Single reference clock frequency for both native SONET and

15/14 (7%) wrapper rate

The device is intended for WDM system applications and can

be used with either an external reference clock or an on-chip

Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz

REFCLK

LVPECL/LVDS/LVCMOS/LVTTL compatible inputs

(LVPECL/LVDS only at 155.52 MHz)

oscillator with external crystal. Both the 2.48 Gb/s and

2.66 Gb/s digital wrapper rates are supported by the ADN2811,

without any change of reference clock.

19.44 MHz on-chip oscillator to be used with external crystal

This device, together with a PIN diode and a TIA preamplifier,

Loss of lock indicator

can implement a highly integrated, low cost, low power, fiber

Loopback mode for high speed test data

optic receiver.

Output squelch and bypass features

Single-supply operation: 3.3 V

Low power: 540 mW typical

7 mm × 7 mm, 48-lead LFCSP

APPLICATIONS

The receiver front end signal detect circuit indicates when the

input signal level has fallen below a user-adjustable threshold.

The signal detect circuit has hysteresis to prevent chatter at the

output.

SONET OC-48, SDH STM-16, and 15/14 FEC

The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead

WDM transponders

chip scale package.

Regenerators/repeaters

Test equipment

Backplane applications

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N

VCC VEE

CF1

CF2

LOL

2

ADN2811

PIN

QUANTIZER

NIN

PHASE

SHIFTER

PHASE

DET.

LOOP

FILTER

VREF

LEVEL

DETECT

THRADJ SDOUT

DATA

RETIMING

2

DATAOUTP/N

2

CLKOUTP/N

LOOP

FILTER

VCO

FREQUENCY

LOCK

DETECTOR

FRACTIONAL

DIVIDER

2

2

/n

XTAL

OSC

REFSEL[0..1]

REFCLKP/N

XO1

XO2

REFSEL

RATE

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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