ADN2812(Rev0) データシートの表示（PDF） - Analog Devices
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ADN2812
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADN2812 Datasheet PDF : 28 Pages
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ADN2812
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
CML OUPUT CHARACTERISTICS
(CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
CML Ouputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
VSE (see Figure 3)
VDIFF (see Figure 3)
VOH
VOL
20% to 80%
80% to 20%
TS (see Figure 2), OC-48
TH (see Figure 2), OC-48
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
(See Figure 11)
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
VIH
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
Min
300
600
VCC − 0.6
150
150
0.7 VCC
−10.0
600
1300
600
600
100
300
20 + 0.1 Cb4
600
1300
12.3
2.0
−5
2.4
Typ
Max
Unit
350
600
mV
700
1200
mV
VCC
V
VCC − 0.35 VCC − 0.3 V
95
112
ps
95
123
ps
200
250
ps
200
250
ps
V
0.3 VCC V
+10.0
µA
0.4
V
400
kHz
ns
ns
ns
ns
ns
ns
300
ns
ns
ns
0
V
VCC
V
100
mV p-p
200
MHz
100
ppm
V
0.8
V
5
µA
µA
V
0.4
V
4 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed (see Table 6).
Rev. 0 | Page 5 of 28
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