EVAL-ADN2812EBZ データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

EVAL-ADN2812EBZ

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2812

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Jitter Specifications ....................................................................... 4

Output and Timing Specifications ............................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

I2C Interface Timing and Internal Register Description ........... 10

Terminology .................................................................................... 12

Input Sensitivity and Input Overdrive ..................................... 12

Single-Ended vs. Differential .................................................... 12

LOS Response Time ................................................................... 12

Jitter Specifications ......................................................................... 13

REVISION HISTORY

3/12—Rev. D to Rev. E

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

5/10—Rev. C to Rev. D

Changes to Figure 4, Table 5 ........................................................... 8

Changes to Figure 24...................................................................... 21

2/09—Rev. B to Rev. C

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

6/07—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Table 6.......................................................................... 11

Data Sheet

Jitter Generation ......................................................................... 13

Jitter Transfer .............................................................................. 13

Jitter Tolerance ............................................................................ 13

Theory of Operation ...................................................................... 14

Functional Description .................................................................. 16

Frequency Acquisition............................................................... 16

Limiting Amplifier ..................................................................... 16

Slice Adjust .................................................................................. 16

LOS Detector .............................................................................. 16

Lock Detector Operation .......................................................... 16

Harmonic Detector .................................................................... 17

Squelch Mode ............................................................................. 17

I2C Interface ................................................................................ 18

Reference Clock (Optional) ...................................................... 18

Applications Information .............................................................. 21

PCB Design Guidelines ............................................................. 21

DC-Coupled Application .......................................................... 23

Coarse Data Rate Readback Look-Up Table............................... 24

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Changes to LTR Mode Description ............................................. 19

Changes to Ordering Guide .......................................................... 26

11/04—Rev. 0 to Rev. A

Change to Specification ....................................................................3

Updated Outline Dimensions ....................................................... 26

Changes to Using the Reference Clock to Lock onto Data

Section.............................................................................................. 19

3/04—Revision 0: Initial Version

Rev. E | Page 2 of 28

Share Link: