ADN2819ACP-CML データシートの表示（PDF） - Analog Devices

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ADN2819ACP-CML

Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

Parameter

Setup Time

Hold Time

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range

Peak-to-Peak Differential Input

Common-Mode Level

TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N)

Peak-to-Peak Differential Input Voltage

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage

Input Low Voltage

Input Current

Input Current (SEL0 and SEL1 Only)5

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage

Output Low Voltage

Conditions

TS (See Figure 3)

OC-48

GbE

OC-12

OC-3

TH (See Figure 3)

OC-48

GbE

OC-12

OC-3

@ REFCLKP or REFCLKN

DC-coupled, single-ended

CML inputs

VIH

VIL

VIN = 0.4 V or VIN = 2.4 V

VIN = 0.4 V or VIN = 2.4 V

VOH, IOH = –2.0 mA

VOL, IOL = +2.0 mA

ADN2819

Min Typ Max Unit

140

ps

350

ps

750

ps

3145

ps

150

ps

350

ps

750

ps

3150

ps

0

VCC V

100

mV

VCC/2

V

0.8

V

2.0 V

–5

–5

0.8 V

+5

µA

+50 µA

2.4

V

0.4 V

1 PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2 PWD measurement made on quantizer outputs in bypass mode.

3 Jitter tolerance measurements are equipment limited.

4 TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

5 SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.

Rev. B | Page 5 of 24

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