ADN2841(2002) データシートの表示（PDF） - Analog Devices
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ADN2841 Datasheet PDF : 12 Pages
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ADN2841
ALARM INTERFACES
A 30 kΩ internal pull-up resistor is employed to pull the digital
high value of the alarm outputs to VCC. However, the ADN2841
has a feature that allows the user to externally wire resistors in
parallel with the 30 kΩ pull-up resistors, thus enabling the user
to interface to non-VCC levels. Non-VCC alarm output levels must
be below the VCC used for the ADN2841.
POWER CONSUMPTION
The ADN2841 die temperature must be kept below 125°C.
The θJA is 25°C/W for the 48-lead LFCSP and 32°C/W for the
32-lead LPCSP when soldered in a four-layered board. Both
LFCSP packages have an exposed paddle and as such need to
be soldered to the PCB to achieve this thermal performance.
TDIE = TAMBIENT + θJA × P
ICC = ICCMIN + 0.3 I MOD
( ) ( ) P =VCC × ICC + I BIAS × VBIAS _ PIN + I MOD ×V MOD _ PIN
Thus the maximum combination of IBIAS + IMOD must be
calculated.
VCC
VCC
IMPD
VCC
ADN2841
ADN2850
IMODP
TX
SDI
RX
SDO DAC1
PSET
IBIAS
CLK
CLK
DAC2
ERSET
CS
CS
DATAP
DATAN
IDTONE
Figure 5. Application Using Optical Supervisor ADN2850
as a Dual 10-Bit Digital Potentiometer Using Thin-Film
Resistor Technology to Give Very Low Temperature
Coefficients
FAIL
VCC
DEGRADE
FU-445SDF-WM1
VCC
VCC
VCC
36
25⍀
VCC
37
CCBIAS
48
VCC
GND2
VCC2
IMODN
IMODN
GND2
IMODP
IMODP
GND2
GND2
IBIAS
IBIAS
1
25
ADN2841
24
GND
GND
CLKN
CLKP
GND1
DATAP
DATAN
GND1
VCC1
GND
PAVCAP
ERCAP
12
GND
13
1.5k⍀
CLKN
CLKP
DATAP
DATAN
VCC
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE
ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED.
100nF 100nF 100nF 100nF 10F
GND
Figure 6. 2.7 Gbps Test Circuit, DC-Coupled, Data Not Clocked, Fast Loop Time Constant Selected
–8–
REV. A
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