ADN2849ACP-RL7 データシートの表示（PDF） - Analog Devices

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ADN2849ACP-RL7

10.7 Gbps Electro-Absorption Modulator Driver

Analog Devices 

Preliminary Technical Data

THEORY OF OPERATION

GENERAL

Figure 17 shows a typical EA modulator characteristic. Vm

represents the voltage across the modulator and Pout represents

the optical output power. For small voltages across the

modulator it is in its high transmission state. As the voltage

becomes more negative, the modulator becomes less

transparent to the laser light. Fig. 17 also shows a typical drive

signal for an EA modulator. It consists of a modulation signal

with a swing Vs, and a bias offset voltage Vb

Pout

GND

DATAP/CLKP

VEE

GND

DATAN/CLKN

VEE

GND

VBB

ADN2849

VEE

50Ω

50Ω

Vm

VEE

VEE

Figure 18. Equivalent circuit for the data and clock input pins

Vs

Vb

Figure 17. Typical transfer function of an EA modulator

As shown in the functional block diagram (figure 1), the

ADN2849 consists of an input stage for data signals, a cross

point adjust block and the output stage that generates the bias

offset and modulation voltages. The retiming option allows the

user to reduce the jitter by applying a reference clock to the

clock inputs of the ADN2849. The cross point adjust block pre-

distorts the data signal applied to the output stage in order to

compensate for the non-linear transfer function of the EA

modulator as shown in figure 17. The modulation and the bias

offset voltage can be programmed via external DC voltages

applied to the ADN2849. These voltages are converted to

currents internally and applied to the output stage. The single-

ended output stage provides both the bias offset and

modulation voltages at the same pin (MODP) without the need

of any external components. The ADN2849 can operate with

positive or negative (5.0V or 5.2V) supply voltage.

INPUT STAGE

The input stage of the ADN2849 gains the data and clock

signals applied to the DATAP, DATAN and CLKP, CLKN pins

respectively to a level that ensures proper operation of the

ADN2849’s output stage. The data and clock inputs are

PECL/CML compatible and can accept input signal swings in

the range of 600mV to 1600mV peak-to peak differential. The

equivalent circuit for the data and clock input pins is shown in

figure 18.

The data and clock input pins are internally terminated with a

100Ω differential termination resistor to minimize signal

reflections at the input pins that could otherwise lead to

degradation in the output eye diagram. The ADN2849 input

pins must be AC-coupled with the signal source to eliminate the

need of matching between the common mode voltages of the

data signal source and the inputs stage of the driver. Also, the

common mode terminal of the internal termination resistors

(VBB) must be externally decoupled. Figure 19 shows the

recommended connection between the data/signal source and

the ADN2849 input pins.

50Ω

50Ω

C

DATAP/CLKP

C

ADN2849

DATAN/CLKN

VBB

C

GND

Data/clock signal source

Figure 19. AC-coupling the data/clock signal source to the ADN2849

input pins

Rev. Pr. G | Page 9 of 17

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