EVAL-ADN2850SDZ データシートの表示（PDF） - Analog Devices
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EVAL-ADN2850SDZ Datasheet PDF : 28 Pages
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Data Sheet
ADN2850
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
SDO 1
GND 2
VSS 3
V1 4
(EXPOSED
PAD)
12 PR
11 WP
10 VDD
9 V2
ADN2850
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
SDO
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
2
GND
Ground Pin, Logic Ground Reference.
3
VSS
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
4
V1
Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
5
W1
Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
6
B1
Terminal B of RDAC1.
7
B2
Terminal B of RDAC2.
8
W2
Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
9
V2
Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
10
VDD
Positive Power Supply.
11
WPE
A
Optional Write Protect. When active low, WPE prevents any changes to the present contents, except PRE strobe.
A
A
A
A
CMD_1
and
COMD_8
refresh
the
RDAC
register
from
EEMEM.
Tie
WPE
A
A
to
VDD,
if
not
used.
12
PRE
A
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale until EEMEM is loaded with a new value by the user. PRE is activated
A
A
at
the
logic
high
transition.
Tie
PRE
A
A
to
VDD,
if
not
used.
13
CSE
A
Serial Register Chip Select Active Low. Serial register operation takes place when CSE returns to logic high.
A
A
14
RDY
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PRE.
A
A
15
CLK
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
16
SDI
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
EP
Exposed Pad. The exposed pad is left floating or is tied to VSS.
Rev. E | Page 9 of 28
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