ADN2890(Rev0) データシートの表示（PDF） - Analog Devices
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ADN2890 Datasheet PDF : 12 Pages
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APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 9, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using filled vias so that solder does not leak through
the vias during reflow. Using filled vias under the package
ADN2890
greatly enhances the reliability of the connectivity of the
exposed pad to the GND plane during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2890 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 12, which supplies power to the
high speed OUTP/OUTN output buffers. Refer to the schematic
in Figure 8 for recommended connections.
VCC
VCC
200Ω
0.1µF
C9
RSSI MEASUREMENT
TO ADC
R1 C10
ADN2880
VCC
C5
C6
16 15 14 13
AVCC
1
DRVCC
12
C1
PIN
2
C2 NIN
3
CONNECT
EXPOSED
PAD TO
GND
OUTP C3
11
OUTN C4
10
AVEE
4
DRVEE
9
5
6
7
8
VCC
C7 C8
TO HOST
BOARD
C11
C12
R2
C1–C4, C11: 0.01µF X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1µF X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE
R3
4.7kΩ TO 10kΩ
ON HOST BOARD
VCC
Figure 8. Typical ADN2890 Applications Circuit
Rev. 0 | Page 9 of 12
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